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Utilising ARM Cortex-M based SoCs (Part 2)

Posted: 28 Jul 2014 ?? ?Print Version ?Bookmark and Share

Keywords:system-on-chips? ARM? Cortex M? SoC? PSoC?

The primary factors determining power consumption are:

Clock speed: In embedded designs, power consumption increases proportionally with an increase in CPU clock speed. ARM processors are designed to provide an optimal balance between power consumption and clock speed.

Applications can be designed to consume less power using an ARM-based SoC by using more efficient instructions (Thumb instructions). These instructions require fewer clocks to execute the same task. Hence, it is possible to clock the design at a lower speed to meet functionality requirements.

Device active time: Again, power consumption increases with an increase in the active time of the processor. This is directly linked to execution time of the processor which, if less, can provide more idle time to the processor.

ARM processors, as discussed earlier, can quickly execute instructions and drop into a low power mode for the time the processor is idle. In this scenario, ARM processors provide better power figures at similar clock speeds.

ARM Cortex-M processors with a Wake-up InterruptController (WIC) enable the processor and Interrupt unit (NVIC) to go to low-power sleep mode. When in sleep mode, the WIC is tasked to identify and schedule interrupts based upon priority. This functionality is implemented using Wait-for-Interrupt (WFI), Wait-for-Event (WFE), and Send Event (SEV) instructions.

Many ARM-based SoC vendors provide power modes that can be used by systems to improve power efficiency. For example, the Cortex-M0-based PSoC 4 provides five power modes to the embedded designers, namely Active, Sleep, Deep Sleep, Hibernate, and Stop, listed in order of decreasing power consumption. Stop mode consumes current in the range of sub-nano amperes.

However, an SoC cannot remain in any single power mode. To reduce average power consumption, different techniques can be deployed.

Stay in low power mode for the majority of the time and enter active mode when a trigger occurs, then execute the exception handler and return to sleep. ARM processors are able to enter low power sleep mode when they returns from an exception handler to thread mode when SLEEPONEXIT is used.

Use the internal SysTick timer to wake up after regular intervals, check the necessary flags, and execute any required tasks.

In addition to accelerating design, lower cost, faster time to market, and broader market applicability for the developer, an ARM-based SoC provides several important advantages, including:

*Simple core design enables ease of integrating it into any SoC

*Area optimised processor C smaller die with reduced dynamic and leakage power

*Processors can be configured during the time of implementation as per requirements:
???Listed configuration options are available to the designer while choosing the ARM Cortex-M core for the SoC to suit the market requirements including:Configurable number of interrupts
???Support of both Endianness (little and big)
???SysTick Timer can be added based on the requirement
???Configurable debug options like Watchpoint comparators, Breakpoint comparators, and halting debug support
???Hardware Multiplier
???Ease of interfacing the processor with different on-chip peripherals

About the authors
Subbarao Lanka is a Staff Applications Engineer working in Cypress Semiconductors on Capacitive Touch Sensing applications since 2007. His responsibilities include defining technical requirements for new capacitive sensing controllers, developing new capacitive sensing controllers, conducting system analysis, debugging technical issues for customers, and technical writing.

Tushar Rastogi worked as Applications Engineer in Cypress Semiconductors. He has worked on PSoC based applications since 2012. His responsibilities include PSoC firmware programming, application development, technical support to customers with programming, and boundary scan related issues and technical writing.

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