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Timing IC integrates clock generators, jitter attenuators

Posted: 31 Jul 2014 ?? ?Print Version ?Bookmark and Share

Keywords:clock? jitter? frequency? networking?

Silicon Labs released what it claims is the most frequency-flexible clock solutions designed to meet the jitter required to support high-speed networking, communications and data centre equipment.

The Si534x "clock-tree-on-a-chip" integrates clock generators and integrated multiplL jitter attenuators, combining all discrete timing functions into a single-chip clock IC solution to reduce the cost and complexity of optical networking, wireless infrastructure, broadband access/aggregation, Carrier Ethernet, test and measurement, and enterprise/data centre equipment including edge routers, switches, storage and servers.

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Block diagram of Si534x. Source: Silicon Labs

The chips provide an I2C-configurable platform featuring a combination of frequency translation capabilities and The company highlighted that the level of integration and frequency flexibility in the chips eliminates the need for multiple clock ICs, discrete level translation, loop filters and power supply filter components. This leads to significantly reduced BOM cost and complexity while still providing more than 50 per cent margin to stringent 10/40/100G jitter specifications.

Simplifying Clock Trees with ClockBuilder Pro

ClockBuilder Pro is designed to help system designers quickly and easily create custom Si534x clocks for their applications. The software boasts an intuitive ClockBuilder Pro GUI with which designers can quickly generate sophisticated device configurations in less than five minutes, minimising software development overhead.

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