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Intel delivers 14nm process technology

Posted: 12 Aug 2014 ?? ?Print Version ?Bookmark and Share

Keywords:14nm? Broadwell? Mark Bohr?

The area shrinks came in part from building taller fins packed more closely together. The shrinks were needed to overcome wafer costs, which rose faster than normal with a new node due to the need for double patterned lithography. Intel rejected the litho etch/litho etch technique, using instead self-aligned double-patterning.

Netting out rising wafer costs and shrinking transistors "for Intel, cost per transistor continues to come down, if anything at a slightly faster rate," said Bohr.

He claimed Intel still has a significant lead over the rest of the chip industry despite delays of nearly a year in shipping 14nm products. "Intel is shipping a second generation of FinFET technology before others shipped their first," he said. With previous planar nodes, "others have tended to have better density than Intel but came to market later," he noted.

 Intel versus industry process technology progress

Bohr's comparison of Intel versus industry process technology progress.

Intel would not comment on when it will have a 14nm smartphone SoC or the impact it hopes Broadwell will have on sales of x86 tablets or notebooks.


Comparing fins

image name

Intel built taller fins packed more closely together to reduce chip area more than normal, compensating for the cost of double patterning.

Tri-gate transistor


Comparing packages

 Comparing packages

Broadwell is 50 per cent smaller in x/y size and 30 per cent smaller in height, in part to accommodate tablets. The package shrink comes in part from more integrated passives (below).

 More integrated passives


Comparing SRAMs

 Comparing SRAMs

Intel crafted a tighter SRAM cell for Broadwell.

- Rick Merritt
??EE Times


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