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Are multi-patterning corners necessary for 16/14 nm?

Posted: 25 Aug 2014 ?? ?Print Version ?Bookmark and Share

Keywords:semiconductor? chip design? multi-patterning corners? verification? colouring?

Now that 16-nm and 14-nm technologies are coming online, and many semiconductor companies are embarking on new chip design projects at those nodes, one question that keeps popping up is whether multi-patterning corners are really necessary.

The cost-layout simulation is frequently a big bottleneck for the verification process, and the more corners that are required, the bigger that bottleneck becomes (figure).

Impact of multi-patterning on extraction
Multi-patterning is the technique required for printing geometries that are smaller than the wavelength of light used in manufacturing can accurately resolve. This is typically limited by both the lenses used and the light sources.

Figure: How many corners are really necessary for chips with multi-patterning? (Source: Mentor Graphics).

To overcome this limitation, polygons on each layer (e.g., metal 1 layer) are split between two or more different masks, as denoted by colour assignments (colouring). Printing polygons using multiple masks makes it possible to print smaller geometries than can be printed with just one mask.

However, one of the drawbacks of using multi-patterning is that it is difficult to precisely align the masks.

Any misalignment has an impact on parasitic capacitance, since some wires will be closer together than they should be, causing higher coupling capacitance, whereas other wires will be farther apart, thereby decreasing coupling capacitance.

For example, a 6 nm misalignment causes a 15% error in coupling capacitance and a 5% error on total capacitance, whereas a 2 nm displacement creates approximately a 5% error for coupling capacitance and 2% error for total capacitance [1]. Foundries try to control this mask misalignment as much as possible, but there will always be some misalignment.

Therefore, it is important to characterise the misalignment by doing simulations with the multi-patterning corners, and making sure that the circuit is robust enough to handle the resulting variation.

Coloured vs. non-coloured parasitic extraction
The parasitic extraction flow to capture multi-patterning effects differs depending on whether or not the layout has already been decomposed into different masks. When deciding on a multi-patterning flow, one major consideration is whether the designer will decompose the layout into the different masks, or whether that step will happen at the foundry.

Different foundries allow different levels of control by their customers for decomposing a layout into multiple masks. Some foundries only require that designs pass multi-patterning space and cycle rule checks, then do the actual decomposition themselves. Other foundries allow customers to tag certain geometries to assign them to a specific mask (a process called anchoring), or even allow customers to fully decompose their designs before tape-out.

If the foundry will do the decomposition themselves, the layout will be colourless, and the parasitic extraction methodology will not have specific information about how polygons are shifted, since the mask assignments are not yet known. In this case, corners can be used to simulate worst-case and best-case capacitance values. For colourless layouts, it is possible to change the dielectric constant to mimic geometric shifts, which assumes that all neighbouring polygons are on opposite masks.

One benefit of using dielectric constant change to mimic physical shifts is that the layout polygons themselves do not actually need to be shifted, saving processing time. However, this approach is less accurate than actually calculating the polygon offset, and calculating the real change in capacitance value.

For partially coloured or fully coloured designs, designers can perform more accurate extraction, since there is knowledge about which polygons are assigned to the same mask.

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