Examining Intel's embedded DRAM

Two major players in the industry—Intel and Samsung—voiced out their disappointment with SRAM scaling at the International Solid-State Circuits Conference (ISSCC) last February.

In the paper Song et. al. from Samsung [1] argued that SRAM not only occupied too much real estate, but the operating voltage did not scale in the same proportion as the logic devices on the same die. Cache size in megabytes was also increasing on the die; so there were more devices on the die that required higher voltages than the main logic part. Hamzaoglu in a paper from Intel [2], revealed that SRAM scaling was not satisfying their requirements and that the majority of the die area was taken by SRAM cell area. The question arose; was it worth continuing to invest in SRAM, especially in 22nm nodes and below, where manufacturing costs were astronomical and could only continue to increase for future technology nodes?

Using fabrication cost and performance data, Intel concluded that an alternative configuration was needed, and therefore opted for an external high-density bandwidth cache memory in the same package. An external memory was easier to fabricate than an embedded SRAM, in an advanced technology process where real-estate was becoming scarce on the die. The DRAM cell was also much smaller than the six transistor SRAM cell layout made at the same lithography node. Moreover, having a separate DRAM die in the same package as the processor reduced chip interface delay, compared with external DRAM in a different package. The eDRAM also required 1/5 of the keep-alive power compared with an SRAM device. This analysis led Intel to release their Haswell processor with an external eDRAM.

The Intel Haswell GT3e G82494 processor came out in the market in October 2013 and was analyzed in our laboratories as part of our TechInsights Award program[3]. Our analysis of the GT3e revealed the general philosophy behind this innovative product—to solve for frustrations experienced with SRAM scaling.

Package
Figure 1, is the package cross-section which shows the processor and the embedded DRAM side by side. The Intel CT3e graphics and GT3e graphics processing unit (GPU) were packaged in a multichip (MCP) process. There were two dice placed side by side and flip-chip bumped to a FR4 type package substrate. One was the eDRAM and the other was the Haswell processor. The eDRAM die area was one third the size of the processor die area. Both dice were flip chip bumped to the package substrate. The die and the package substrate were connected together by Cu-pillars. The same packaging process was used by Intel 32nm and 22nm logic processes.

Embedded DRAM's process integration designed to facilitate further scaling
The Intel eDRAM embedded in the Intel GT3e graphics processing unit, and used by the Haswell G82494 processor, was fabricated using nine levels of metallization with 22 nm Tri-Gate transistor technologies. The Intel eDRAM die, in GT3e GPU, also used the manufacturing proven multi-layer replacement metal gate process seen in their Ivy Bridge device. Silicon source/drain regions were used for the NMOS transistors and SiGe for the PMOS transistors. The embedded DRAM cell was 0.029?m² large. The cell capacitors were formed in trenches patterned through the ILD dielectrics supporting the metal 3 and metal 4 interconnects. Gate last high-k metal gate (HKMG) finFET transistors were used for the eDRAM access transistors having a 107 nm wordline pitch. Figure 2 depicts a general overview of the embedded DRAM. The capacitor trench bottoms were supported by the via 1 and metal 2 Ta-based barrier layer.

The Intel eDRAM device used a twin-well process for the eDRAM array access transistors. The device did not appear to use an embedded well process, as the transistor's channel was decoupled from the substrate, yielding threshold voltages that were independent of well bias. FinFETS transistors have a limitation that they have a quantized width so gate widths were increased by adding fins in parallel to the transistor. Intel employed a finer pitch for peripheral logic and more relaxed pitch for the NMOS access transistors in the eDRAM region. A relaxed pattern was used in eDRAM region to give low I_off leakage currents in DRAM access transistors.