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Memory process roadmap soldiers on amid looming 3D tech

Posted: 26 Aug 2014 ?? ?Print Version ?Bookmark and Share

Keywords:IC Insights? process roadmap? memory? NAND? DRAM?

There is presently a continuous effort to extend the life of DRAM and NAND flash as alternative memories for a number of applications. The constant reduction in feature sizes used to manufacture ICs has improved memory-chip performance by increasing per-chip storage capacities, lowering power consumption, and improving the speed in which memory devices can store and retrieve data (i.e., memory bandwidth). For instance, there has been nearly 20 times improvement in the per-channel memory bandwidth of mobile DRAM over the past decade.

In mid-2014, the most advanced process technology used to make NAND flash devices was based on 20nm and smaller feature sizes, and just under 30nm for DRAMs. The process technology roadmaps suggest that by 2017, the minimum feature size for 2D (planar) NAND flash will migrate to 10-12nm and to ?20nm for DRAM. The transition points shown in the chart should be used only as rough guidelines since reported minimum feature sizes and mass production definitions are very imprecise and may be influenced by marketing "numbers games" as companies strive to get ahead of the competition.

In manufacturing NAND flash memory, companies such as Samsung, SK Hynix, Toshiba and IM Flash Technologies are applying minimum geometries of 15-16nm. The first of these NAND devices were built in 2H13, but production quantities were limited amid reports of initial yield challenges. However, high-volume production of 15-16nm NAND chips has been ramping up in 2014.

SanDisk announced that the generation following its 19nm-based NAND chips (some call it the 1y generation that follows 1x) would have the same minimum geometry (19nm) as the prior generation. It was expected that SanDisk's 1y NAND chips would have a minimum geometry of 15-16nm. Though the minimum feature size remained the same, SanDisk was able to reduce the memory cell size by 25 per cent. Initial production of the 1y devices started in 2H13. It appears that SanDisk (and its manufacturing partner Toshiba) decided to improve the cell size through advanced memory cell design efforts instead of scaling the geometry.

IM Flash, the memory-chip joint venture between Intel and Micron, said it believes 2D NAND flash technology could be scaled to 10nm and that 3D NAND would take over from there. The company also said that 3D NAND would have to be manufactured with at least 32 layers to be economically feasible.

NAND Flash process roadmaps

The first company to mass-produce 3D NAND chips was Samsung. In May 2014, the company announced that it had started volume production of its V-NAND flash chips using 32 memory cell layers. The company had previously shipped a limited number of solid-state drives (SSDs) based on its first generation 24-layer V-NAND technology to some of its data centre customers in 2013. In conjunction with the 32-layer V NAND announcement, Samsung launched a line-up of premium SSDs based on the second-generation technology that are available for not just data centre applications, but also for high-end personal computers.

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