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Power tip: How to get more power from a flyback

Posted: 05 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:power supply? flyback? power dissipations? interleaved? single-phase?

Among power supply topologies, the flyback is considered the work-horse. It works quite well for a wide range of inputs, low to medium power levels, and high-voltage inputs and outputs. Semiconductor component count is low as there is only a primary switch and output rectifier. It is, however, power limited due to the high currents that it generates. Its usefulness is usually limited to less than 100 watts. Above this power level, designers start considering other topologies.

In high-power flybacks, the power dissipations in the semiconductors are high enough that single packages for each are no longer viable. Multiple parallel packages may be used, but balancing current to equalise the temperature becomes an issue.

Buck regulators use multiple phases to mitigate this issue. Power stages are repeated and the inputs and outputs have common connections. The phases are offset in time to provide capacitor ripple current cancellation and a higher effective switching frequency. This same technique can be employed with the flyback as shown in figure 1. The top schematic shows the familiar flyback in its simplicity while the bottom schematic shows the interleaved design.

Figure 1: Capacitor ripple currents are significantly less with interleaving.

At first glance, the interleaved design has twice as many components. But when using this method, you generally will be delivering more power than a single package could sustain in the single-phase design, so the component count will be similar between the two.

On the chart to the right of the schematic we have the capacitor ripple currents, red for the single-phase design and blue for the interleaved. Ripple current in the single-phase design is positive when the power switch is on, and negative to recharge the capacitor when the switch is off. It is worst-case at 50% operation when the reset voltage on the transformer is equal to the input voltage. For the interleaved design, this is the best case. The two phases are drawing currents at 180 difference and the ripple currents completely cancel.

Figure 2 shows the ripple current variation over a wide line range. These curves have been generated with the assumptions of 50% maximum duty factor and the reset voltage equal to the minimum line voltage. This figure has been normalized in a couple ways. The horizontal axis normalizes the input voltage by the reset voltage and shows a 4:1 line range indicative of a universal input.

Figure 2: Input capacitor ripple current is 2/3 less with two phases.

The vertical axis normalizes the RMS current in the input capacitor divided by the DC input current at low-line (which in this assumption equals the reset voltage). As shown in the previous figure, the RMS input current for the single-phase design is worst case at a duty factor of 50%, which corresponds to an input voltage equal to the reset voltage (VIN/VRESET= 1).

At this condition in the two-phase design, the two power-stage currents cancel each other resulting in zero AC current in the input bypass capacitor. To establish ripple ratios between the two, the worst case single-phase ripple point is a normalized ratio of 1. For the two-phase, the worst ratio is about one third. In other words, if you were picking input capacitors based on ripple current rating, the two-phase design uses one third the capacitors of the single-phase design.

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