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DDR3 design requirements for KeyStone DSP

Posted: 10 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:DDR3? interface? Texas Instruments? KeyStone? DSP?

This application note provides implementation instructions for the DDR3 interface incorporated in the Texas Instruments (TI) KeyStone series of DSP devices. The DDR3 interface supports 1600 MT/s and lower memory speeds in a variety of topologies (see the specific device Data Manual for supported speeds). This document assumes the user has a familiarisation with DRAM implementation concepts and constraints.

View the PDF document for more information.

Originally published by Texas Instruments Inc. at www.ti.com as "DDR3 Design Requirements for KeyStone Devices".





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