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Initialising KeyStone I DDR3

Posted: 11 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:DDR3? interface? Texas Instruments? KeyStone? DSP?

The initialisation of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.

All DDR3 initialisation routines must contain the basic register writes to configure the memory controller within the DSP as well as register writes that configure the mode registers within the attached DRAM devices. The datasheet for the DRAM implemented must be referenced to optimise these values. In addition, because DDR3 implementations use a fly-by routing topology, PCB track lengths for the fly-by signals (Address, Command, Control, and Clock) and data group signals (DQ, DQS, and DQM) must be available to properly initialise the leveling registers.

View the PDF document for more information.

Originally published by Texas Instruments Inc. at www.ti.com as "KeyStone I DDR3 Initialization".





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