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Samsung funds research for 7nm

Posted: 03 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:III-V? FinFET? InGaAs? 7nm?

Samsung is investing in Pennsylvania State University for its work on fabricating III-V indium gallium arsenide FinFETs likely to be used at the 7nm node.

The silicon FinFET (3D fin gates on field effect transistors) have become the standard for low leakage and high performance at advanced nodes, but III-V compounds such as indium gallium arsenide (InGaAs) are faster than silicon, prompting researchers at Penn State to combine the best of both worlds. Penn State's InGaAs FinFET transistors use a novel five-gate structure grown on an indium phosphide (InP) substrate in its Materials Research Institute's Nanofabrication Laboratory.

"These FinFETs as of now have been fabricated on InP substrates," Arun Thathachary, an EE doctoral candidate working under Professor Suman Datta, told EE Times. "Samsung will own the IP generated from this project." Fellow doctoral candidate Nidhi Agrawal has also contributed to the project.

Imec demos III-V FinFET devices on 300mm Si wafers
The devices enable continual CMOS scaling down to 7nm and below, and also enable new heterogeneous system opportunities in hybrid CMOS-RF and CMOS-optoelectronics.

For years, other semiconductor firms have funded research to fabricate III-V transistors on silicon substrates, including Intel, Sematech, and, more recently, Imec.

The reason everybody is trying to integrate III-V transistor channels with silicon substrates is cost. Not only are InP wafers more expensive, but the entire semiconductor industry is based on equipment optimised for silicon manufacturing. So even though Penn State is using InP wafers to prove the concept that III-V FinFETs will retain their high mobility at advanced nodes (5nm) and at lower voltages (0.5V), Samsung would eventually have to solve the problems of integrating III-V materials with complementary (n- and p-channel) metal-oxide semiconductors (CMOS) on 300mm silicon substrates.

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Scanning electron microscope micrograph of a multi-gate indium gallium arsenide (InGaAs) FET using an array of five 40nm-wide nanowires. Source: Penn State

Thathachary told EE Times:

This entire research project is being sponsored by Samsung with the sole purpose of investigating III-V materials for low-power CMOS manufacturing. But as far as integration on 300mm silicon goes, there are significant growth challenges involved in engineering the buffer layers. Though there have been several publications in this regard over the last couple of years, a high-yield solution for 300mm manufacturing is still lacking. Additionally, III-V materials only provide excellent electron mobility, which means n-channel only. For p-channel devices, there is a significant effort in co-integrating germanium channels alongside III-V to facilitate 300mm CMOS manufacturing. This is also being actively investigated by several companies and consortia, including Imec and Sematech.

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