Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Networks

64bit revenge: ARM returns to server market

Posted: 02 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:ARMv8? 64bit? server? datacentre?

Bloodied but not unbowed, ARM has taken a hit in the server market when Calxedaonce known as the bearer of ARM architecture for datacentrescollapsed in 2013. But the ecosystem is turning the corner, getting support from the popular ARMv8 64bit.

It turns out four out of the top five companies that provide chips for enterprise networking and servers are working on ARM-based devices, and with key players like Cavium and AMD in the mix for the first time, there is plenty of optimism.

The 50th licensing agreement for the 64bit-capable ARM Cortex-A50 processor family and ARMv8 architecture licences since November 2011 includes these key infrastructure deployments coping with more complex applications within strict power budgets:

image name

AMD's Opteron 1100 Seattle combines eight A57 cores for server applications.

The details of the ARM Opteron A1100 show eight 64bit cores with L3 cache on chip, with a lowly A5 core in the corner as an "SoC in an SoC" to handle the legacy peripherals. Meanwhile the heavy lifting for communications across devices and cards is handled by eight lanes of x8 PCI-Express and two 10GBase-KR Ethernet ports for a direct connection to the copper of the backplane. The focus on the memory and the peripherals makes it very different from the massively multi-core networking devices.

Cavium has long been a MIPS house with its Octeon III CN7xxx family based on the MIPS64 architecture, but with the collapse of Calxeda it took on co-founder Larry Wikelius and former colleague Gopal Hegde. As a result we are seeing a family of processors with 24 to 48 64bit A50 ARM cores on a 28nm process due for the end of this year. Calvium says the ThunderX CN88XX family is the first ARM-based SoC that scales up to 48 cores with up to 2.5GHz core frequency with 78k of I-Cache and 32k of D-Cache along with 16MB of L2 cache. It is also lays claim to the first ARM-based SOC to be fully cache coherent across dual sockets using Cavium Coherent Processor Interconnect (CCPI), while the four DDR3/4 72bit memory controllers are capable of supporting 2,400MHz memories with 1TB of memory in a dual-socket configuration

1???2?Next Page?Last Page

Article Comments - 64bit revenge: ARM returns to server...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top