Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Memory/Storage

DDR memory IP boasts innovative adaptive tech

Posted: 05 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Uniquify? DDR memory? broadband? cellular? DSL?

Uniquify has revealed that its adaptive DDR memory subsystem intellectual property (IP), recently established as the fastest DDR4 clocking 2800Mb/s in a 28nm process technology, has been licensed to a number of companies in many of the semiconductor industry's fastest growing market segments. Each company selected the company's DDR memory subsystem IP for its innovative adaptive technology: self-calibrating logic (SCL) and dynamic SCL (DSCL) for real-time static and dynamic timing calibration.

The market segments range from broadband, cellular communications and DSL to high definition TV (HDTV), image processing, networking, test and measurement and video equipment.

SoC designs integrate DDR memory IP that operate at multi-GHz clock rates with read-write timing margins measured in picoseconds. Designing the DDR memory IP to accommodate variations in system-level timing parameters during read and write cycles can require exhaustive rounds of incremental tuning that can cause suboptimal system yield in volume production.

Uniquify's SCL technology solves this problem by performing automatic self-calibration at system power-up for optimal DDR interface timing. SCL-enhanced DDR memory IP offers higher yield because it automatically adapts critical timing characteristics for a wide range of system-level design choices and for variations in the SoC and DDR memory processes.

The DSCL technology builds on SCL by extending the precise timing calibration to execute dynamically during system operation. This is how a 28nm DDR4 system was able to achieve performance of 2800Mb/s when operating with an SDRAM rated for 2400Mb/s operation. During system operation, temperature and supply voltages vary over time, degrading DDR memory performance and causing potential intermittent memory subsystem failure.

DSCL automatically re-calibrates the critical DDR memory interface timing at user-specified intervals during system operation and is set to operate during periods of low memory activity for negligible impact on system throughput. The DSCL calibration is fast and the hardware required to support the addition of DSCL is minimal. In fact, the addition of DSCL results in a smaller DDR PHY since it obviates the need for other synchronising hardware that is required in the traditional (non-DSCL) PHY architecture such as FIFOs, noted the company.

Article Comments - DDR memory IP boasts innovative adap...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top