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When sub-systems are more than just bigger IP

Posted: 11 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:sub-system? IP? GenSys? ARM? GPU?

I have been asked this question several times: When is a sub-system not like an IP? However, I haven't had a good answer until recently. A change in adoption of one of our tools led me circuitously to a cause, and also to an interesting trend in SoC design. The change is new growth in use of our GenSys tool in the assembly and optimisation of sub-systemsparticularly ARM and GPU sub-systems. Tracing back from that effect to the root cause has taken some detective work. In the process, I gained a better understanding of what makes sub-systems more than just "bigger IP."



Figure 1: A typical starting pointan ARM Cortex-A57 sub-system. This includes a multi-core CPU and multiple caches, as well as a bus interface to external logic.

The design task in using this sub-system can be broken down into two components as follows:

???The sub-system must be configured for use in SoCs, which almost certainly do not follow ARM standards. ARM provides the means to configure some number of slave interfaces with certain protocols, butoutside the sub-systemyou will very probably use local bus protocols or your own flavour of AMBA. Your SoC integration teams are experienced in working with these protocols, not the ARM protocol (even if you use the AMBA protocol internallyunless you use the ARM version of the AMBA generator, you are using your own flavour of AMBA). Therefore you have to wrap the sub-system in adaptation logicbus adaptors at minimum, possibly also configuration registers adapted to local standards and so onwhatever is needed to provide a standard "localized" package to all integrators.
???The sub-system must be tuned to give the absolute best Power, Performance, Area/Cost, and Reliability (PPAR). While common IP platforms have unquestionable upsides, one downside is that most competitors for any given application are building their products around the same components. Since these contribute significantly to your overall product PPAR, how do you differentiate (aside from whatever secret sauce you add), orat leastnot fall behind? The only possible way in hardware is through superior implementationyou optimise for the very best PPAR you can get, which means you need to turn this whole thing into a hard macro. It is well-known that, where a basic full-chip ARM-based implementation may run at say 500MHz, a finely-tuned hard macro can run at 3GHz or higher, probably in a smaller area if carefully tiled. And, since this will be a hard macro, it has to be finished for whatever power management, test, and other logic you have planned, and it must be optimised to the floorplan of the targeted SoC.

Figure 2: Adapting and finishing the sub-system.

So far, so good. But this adaptation, PPAR tuning, finishing, and implementation takes a lot of expertise in tools, in ARM IP, in protocols and sub-systems, and also in your local protocols and technology needs. And, since many of your current products use ARM sub-systems, it makes sense to form a central design team responsible to leverage that expertise to all consumers of these hard macros. But there's a catch. The end-product needs are similar, but not identical. Each product must be as competitive as it possibly can be in its respective market. That drives a different functional and PPAR profile for each sub-system usage. A very simple and obvious example is the detailed pinout and consequent constraints on the layout. What will work well for one SoC may need to be changed significantly for another. So now your central team needs to pump out optimised hard macros at a very fast rate to keep up with your product launch rate.

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