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Intel plans to extend Moore's Law to 7nm

Posted: 12 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:7nm? 10nm? lithography? 2.5D? EUV?

Even without long-delayed advances in lithography, Intel is keen on driving Moore's Law down to 7nm. It also gave its most detailed look to date at its foundry service for sharing its chipmaking prowess, including a description of a new low-cost alternative to 2.5D chip stacking it has in development.

"My day job is working on [research for a process to make] 7nm [chips and] I believe there is a way without EUV," said Intel fellow Mark Bohr, responding to a question after a talk on Intel's new 14nm process.

Mark Bohr

The optimism is significant given the core lithography used for patterning chips hasn't had an upgrade in more than a decade. Chipmakers generally don't expect the much-delayed extreme ultraviolet (EUV) lithography in time for 10nm chips, but many still hold out hopes it could be ready for a 7nm generation. (See related news on 7nm node.)

"I am very interested in EUV [because it] could really help scaling and perhaps process simplification, reducing three or four masks to one in some cases," Bohr said. "Unfortunately, it's not ready yetthe throughput and reliability are not there."

Bohr did not give any hints about how Intel will make 7nm or even 10nm chips without EUV. However, he did note at 14nm Intel is using triple patterning on one or more critical layers.

Although wafer costs rose at an accelerating rate for the last two nodes due to the need for more masks, Intel continues to pack more transistors in a given area of silicon. The density offsets wafer costs, leading to the cost-per-transistor decline, Bohr said in his talk on Intel's 14nm process.

"One of the fundamental benefits of Moore's Law is smaller feature sizes, primarily to get lower cost per transistor so we can do more things" in a similarly sized chip, he said.

Intel already announced it has started making in volume chips using a 14nm process at a lower cost per transistor than its prior 22nm generation. It also said it is in development of a 10nm process that it believes will deliver lower cost per transistor.

In a separate talk, Intel said before the end of 2015 it could offer external foundry customers a chance to try out its emerging 10nm process on shared wafers called shuttles.

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