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Intel plans to extend Moore's Law to 7nm

Posted: 12 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:7nm? 10nm? lithography? 2.5D? EUV?

Inside Intel's foundry service

In his most detailed talk to date, Sunit Rikhi, general manager of Intel's custom foundry business, described the details of an end-to-end service that's now more open than ever but still evolving.

Customers are currently using their own designs, supplemented with some IP blocks from Synopsys and Cadence. In the future, Intel will offer some IP, starting with an Atom core still in development.

"Today we do not have an [Intel] IP catalogue. We know there is a large amount of energy to make truly pluggable IP in the form customers are used to, and we have started giving it the engineering focus it needs," said Rikhi.

Users can design with customer-owned tooling or choose from third-party tools from Ansys, Cadence, Mentor Graphics, and Synopsys that Intel has qualified. Each step in the flow varies, with sometimes only one and sometimes several tool choices available.

Sunit Rikhi

The foundry's initial 22nm offering comes in just one flavour. Starting at 14nm, Intel is offering general-purpose and low-power flavours with a family of transistors geared for high performance or low leakage needs.

Intel will provide a wide range of engineering services including chip design, packaging, and use of its in-house designed testing systems. The company recently revealed it builds its own chip test systems and test methods in house, claiming it shaves in half costs of using external gear.

"It's a very significant benefit, and more than a cost reduction; it's a systematic interface... for testing increasingly complex products in an engineering lab and taking them quickly to production," Rikhi said.

The company has two customers now in volume production with a third ramping. It has more than the six customers it has publicly announced, including one that signed on after the announcement of Panasonic in July.

"Our ability to keep cost of transistors going down by more than the normal area scaling is unique, and our customers appreciate it," said Rikhi.

Low-cost alternative to 2.5D stacks

Most significantly, Intel is far along in testing a lower-cost alternative to 2.5D chip stacks it calls the Embedded Multi-Die Interconnect Bridge.

 EMIB packages

Intel has prototyped EMIB packages with more than five dies.

Unlike the 2.5D process, EMIB does not lay dies side-by-side on large silicon interposers, connecting them with through silicon vias (TSVs). Instead it uses a more conventional kind of flip chip process with metal bump interconnects inside a package.

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