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Intel plans to extend Moore's Law to 7nm

Posted: 12 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:7nm? 10nm? lithography? 2.5D? EUV?

EMIB employs back-end-of-line metallisation and wafer thinning techniques used in a 2.5D stack. However, by eliminating TSVs it significantly reduces costs, including costs of wasted die, Rikhi said. The process offers interconnects that are as dense and fast as TSVs, he added.

Intel has prototyped chips with "far north of five die" linked in an EMIB package. It expects to sample the technique to foundry customers in 2015.

Interestingly, Rikhi said Intel currently has nothing in development for foundry customers interested in creating memory stacks using so-called high bandwidth memory such as Micron's Hybrid Memory Cube.


EMIB is less costly than 2.5D stacks, with no loss in interconnect density or speed, according to Sunit Rikhi.

If Intel's claims are true, it is reaping benefits at levels few others in the industry expect to see, a fact that could fuel its emerging foundry business and further widen its lead over competitors. Nevertheless, analysts gave Intel's emerging foundry service mixed reviews.

Intel's foundry costs are still unknown outside its current customers and may carry a steep premium over existing foundries, said Richard Doherty of Envisioneering. In addition, he noted only two customers are now in volume production through the effort started several years ago.

"One thing they don't talk about is parametric yields," said Handel Jones, principal of International Business Strategies. "It took them 18 months to address that" at the 14nm node.

 EMIB design

Another look at an Intel EMIB design.

However, Jones added, "We still think they have an 18- to 24-month lead on other foundries in terms of manufacturing high volumes with reductions in cost per transistor."

- Rick Merritt
??EE Times Asia

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