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Toshiba TFETs promise MCUs ultra-low power edge

Posted: 12 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:TFET? MCU? ultra-low power? quantum tunnelling? MOSFET?

Toshiba Corp. said it has successfully developed Tunnelling Field Effect Transistors (TFETs) for building ultra-low power MCUs. When applied into some circuit blocks, the TFETs could significantly cut power consumption in MCUs.

The Toshiba TFETs are fabricated using a quantum tunnelling principle to achieve ultra-low power LSI operation as a substitute to the conventional MOSFETs.

In simple terms, TFET is a gated p-i-n diode operating under reverse bias condition, according to Rahim Esfandyarpour of Stanford University. While a MOSFET uses thermal injection as a source of carrier injection mechanism, TFET utilises band-to-band tunnelling. Esfandyarpour said that the tunnelling technique enables sub-60-mV/dec S (where S is the sub threshold slope), showing the feasibility of the TFET for low-power applications.

The introduction of new materials such as III-V compound semiconductors led to studies exploring its potential for fabricating TFETs since such materials exhibit properties likely to provide high performance. However, it is difficult to implement them into current CMOS platforms due to the difficulties resulting from special process utilisation.

In addressing this problem, Toshiba optimised TFET properties for some of key circuit blocks using common CMOS process. This approach enables simple installation of TFET into existing production line.

Toshiba has developed two types of Si-based TFET, one for logic circuits with ultra-low leakage current and optimised ON current, the other for SRAM circuits with extremely low transistor characteristics variation. Both utilise vertical type tunnelling operation to enhance tunnelling properties.

In addition, the logic TFET employs precisely controlled epitaxial material growth process for tunnel junction formation with carbon and phosphorus doped Si. The Si/SiGe hetero junction has also been comprehensively evaluated to secure optimised configuration.

The resulting device achieves an ON current two orders of magnitude higher than a Si TFET, which keeps same ultra-low OFF current, both in N and P-type TFET. For the SRAM type TFET development, Toshiba has proposed novel TFET operation architecture which doesn't need to form a structural tunnel junction. It eliminates process variability and results in significantly suppressed transistor characteristics variation.

Toshiba is currently planning to integrate these TFETs with conventional MOSFETs in an MCU to reduce total power consumption by one-tenth or more, targeting commercial production and use by 2017.

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