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Squeezing in Moore: Steppers for 10nm, EUV for 7nm

Posted: 17 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:EUV? lithography? 10nm? 7nm?

Stepper-maker ASML now acknowledge what its customers have long been considering about fabricating 10mm chipsthat companies will use traditional immersion lithography instead of the long-delayed extreme ultraviolet (EUV) systems.

However, that will make the 10nm node an unpopular one that is pressed to deliver lower costs per transistor. Most critical layers will require three or even four exposures, said ASML President & CTO Martin Van den Brink.

"10nm will be a squeezed node that no one will like, due to insufficient cost reduction, but there will be enough cost reduction to let it go forward," Van den Brink said.

For the follow-on 7nm generation, chipmakers will need to use EUV to make chips cost effectively, he insisted. Without it some layers would require as many as 13 passes through an immersion stepper, he told us.

7nm vs 10nm

Without EUV, the 7nm node (far right) could require patterning some layers as many as 13 times, ASML claims. The 10nm node (second from right) will need triple and quad patterning at many layers, Van den Brink said.

Van den Brink made his comments at the ASML office just a block away from the headquarters of one of his largest customers, Intel. Last week, Intel Fellow Mark Bohr said the CPU giant has found a way to make its 7nm chips without EUV (see Intel plans to extend Moore's Law to 7nm.

"My full-time job is researching 7nm, and I would like to have [EUV] but I cannot bet my career or Intel's future on it... [and] 7nm is doable in my opinion without EUV."

Intel's 7nm node is really what the rest of the industry considers a 10nm node, Van den Brink countered. Intel has jumped a node ahead of the rest of the industry in how it names its processes, but the underlying resolutions used by Intel and its rivals are essentially the same at any given point in time because they are using the same litho machines, he argued.

The way nodes get named has become opaque given the rising complexity of the underlying processes, he said. "It's all part of the marketing todayit's too convoluted."

EUV makes slow progress

Mask makers need to ramp up support for EUV by 2016 when many chip makers will start qualifying EUV systems on a 10nm process. Fabs will test out EUV at 10nm but not put it into production until they ramp their 7nm nodes, Van den Brink told EE Times. Nevertheless the tools promise a lifetime of at least a decade.

7nm vs 10nm

ASML aims to match litho targets to the silicon road map.

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