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Designing UART in MyHDL and testing it in FPGA

Posted: 24 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:universal asynchronous receiver/transmitter? UART? MyHDL? VHDL? Verilog?

The @always_seq is a MyHDL decorator. It's analogous to a VHDL process or a Verilog @always. There are several decorators in MyHDL; this one creates a synchronous process with a clock and a reset. The .next is a function that indicates that the value is going to be updated in the next delta cycle, which is again analogous to processes in VHDL and Verilog. It's necessary to return our decorators at the end of the process.

The serial_tx module
We have a state machine that waits for a start signal (start_i) to initialise and send our byte (data_i) via the TX line (transmit_o).

We describe everything at the RTL level. Once again, the MyHDL code is very similar to its VHDL and Verilog counterparts. We now also have an @always_comb decorator, which is equivalent to a purely combinational Verilog always or a VHDL process. We send a bit at each baud rate "tick." I've used a dual state machine approach to separate the combinational and sequential partsthe registers are inferred by the @always_seq decorator.

The serial_rx module
In this case, we wait for a start bit, and then we store the next byte in a register. This approach is very similar to the way in which we implemented the serial_tx module.

Creating the testbench
Let's start by creating a traditional testbench for our design, excite it, and check (cheque for banks) the waveforms.

We'll import the modules that we've just created (,, and into the file

We first define our custom header. (As most companies enforce header, it's good to be able to customise your own.)

We then define our bench function, which is going to test our modules. We start with the constant declarations, like our clk_period, clk_freq, and baud_const. All the signals that connect our modules together are also declared. (Pay attention to the declaration order.)

All the @always_seq decorators that are connected to our reset signal are going to behave like the reset's parameters (active at 0 and async).

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