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Designing UART in MyHDL and testing it in FPGA

Posted: 24 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:universal asynchronous receiver/transmitter? UART? MyHDL? VHDL? Verilog?

Next we have two decoratorsone to generate our clock and the other to generate the stimulus. As we can see, we are getting the data 196 (hexadecimal: c4) at our serial_tx and sending it. We hope that our serial_rx module will return 196 when the rx_rdy signal goes to 1.

The yield keyword is equivalent to a wait in VHDL; when the condition becomes true, the execution continues.

Our test_bench function executes the bench. TraceSignals is our function responsible for the waveform generation in a .vcd file. Let's run our simulation for 1 ms by executing the following command:


This will cause a bench.vcd to be created. Let's open this file using the free, open-source gtkwave tool as follows:

>gtkwave bench.vd

And there is our data sent and received. Everything seems to work.

Test automation
One advantage of MyHDL is the ability to automate our tests. We no longer have to spend countless hours staring at waveforms to see if everything is working as expected.

For example, suppose that, in order to verify that everything is working as expected, we wait for the rx_rdy posedge and then check (cheque for banks) to see if the data we transmitted is the same as the data we received. In order to do this, add these two lines after the line = 0; and don't forget to keep the indentation, because Python is indentation based.

And then we run the py.test framework at the terminal.


And Voil! As we see, MyHDL automatically checks that the transmitted and received data are identical following the rising edge of the rx_rdy signal.

Generating VHDL and/or Verilog code
So everything is working, and now we want to test our design in an FPGA to see how it performs in the real world. MyHDL can't be synthesised directly, so we have to generate the equivalent VHDL or Verilog files. Fortunately, this is very easy. All we have to do is change the following statement in our file (note especially the use of the toVHDL() function):

We also have to make the following change:

If we wanted to generate Verilog, all we would have to do would be replace the calls to the toVHDL() function with the toVerilog() equivalent.

Generally speaking, the resulting VHDL/Verilog is very legible and well structured. Of course, since the generated output is basically a translation of your RTL in Python, any bad Python will result in equally bad VHDL/Verilog. As an example, let's look at our generated serial_tx.vhd as shown below:

Testing on the FPGA board
I have a DE2-70 and a USB -> serial cable as shown below:

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