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SerDes platform speeds deployment of 100G network chips

Posted: 18 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Open-Silicon? SerDes? Semtech? 100G network? analogue front end?

Open-Silicon has released a 28Gb/s serializer/deserializer (SerDes) evaluation platform for ASIC development that will allow the rapid deployment of chips and systems for 100G networks. According to the company, the platform includes a full board with packaged 28nm test chip, software and characterisation data. The chip integrates a 28Gb/s SerDes quad macro, using PHY IP from Semtech, and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications.

The Semtech SBMULTC2T28HPM28G PHY has an analogue front end (AFE) that includes the transmit (Tx) and receive (Rx) path circuitry along with auxiliary blocks for clock generation, test and biasing. The Tx driver is a highly programmable block including multiple registers to allow adjustment of TX amplitude, de-emphasis and pre-emphasis. The PHY can be programmed to support multiple standards each with specific electrical performance characteristics. The area, power and latency have been optimised for SoCs, ASICs or ASSPs. A post-silicon tuning capability allows customers to adapt the performance of the PHY to different operating environments.

As part of the Open-Silicon SerDes Technology Centre of Excellence (TcoE) offering, the 28G SerDes is targeted for ASIC and SoC deployment in high-data-rate, chip-to-chip and chip-to-module applications. Open-Silicon applies its unique, high-speed serial design expertise to ensure the successful delivery of ASICs and SoCs for next-generation, high-speed systems used in the networking, telecom, computing and storage markets, sated the company.

The 28nm test chip has been packaged in a 19 x 19mm, 324-ball high performance low temperature co-fired ceramic (LTCC) flipchip substrate. This package material was selected for its relatively wider trace characteristics, low loss tangent and superior uniform via arrangements that minimise reflections in vertical transitions. Open-Silicon optimised the final package design through simulations to meet and exceed the guidance derived from the CEI specifications.

The 28Gbps SerDes evaluation platform will be available by the end of Q3 from Open-Silicon.

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