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Synopsys platform speeds up time-to-market for advanced SoCs

Posted: 25 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? SoC design? verification? FPGA? Internet of Things?

Synopsys Inc. has revealed the Synopsys Verification Continuum platform that aims to speed up industry innovation for earlier software bring-up and shorter time-to-market for advanced SoCs. The platform is built from Synopsys' verification technologies providing virtual prototyping, static and formal verification, simulation, emulation, FPGA-based prototyping and debug in a unified environment with verification IP, planning and coverage technology.

Verification Continuum introduces Unified Compile with VCS and Unified Debug with Verdi across the verification flow, speeding time-to-market by months for complex SoC designs, added the company.

The mobile and Internet of Things (IoT) markets are driving dramatic increases in SoC complexity and software content along with intensifying time-to-market pressure. To address these challenges, SoC teams require many verification technologies such as simulation, emulation and prototyping across the spectrum of pre-silicon verification, post-silicon validation and early software bring-up. Today engineers spend months of effort in design bring-up and transition effort between disjoint technologies, further complicated by the need to debug across domains and to support large software teams. To shorten SoC time-to-market, leading teams are adopting "shift-left" strategies with concurrent practices across pre-silicon verification, post-silicon validation and software bring-up. Synopsys' Verification Continuum enables these shift-left strategies with best-in-class verification technologies unified with seamless design bring-up, transition and debug throughout the flow.

Synopsys' Verification Continuum is built from the industry's fastest verification engines including Virtualiser virtual prototyping, Verification Compiler static and formal technologies, VCS simulation, ZeBu emulation, HAPS FPGA-based prototyping and Verdi3 debug, detailed the company. These technologies claim to offer the performance and capacity that industry leaders depend on to verify many of the world's largest and most complex chips.

Verification Continuum features Unified Compile based on the mature VCS simulator front-end, providing a robust simulation-like user experience across the verification flow, that enables engineers to easily transition between simulation, static and formal verification, emulation, FPGA-based prototyping and debug as required by the verification task. Existing flows based on individual point tools require extensive setup for each tool in the flow, and weeks or months of effort to move a design between different tools based on varying language support or other requirements. Unified Compile with VCS eliminates this redundant work, saving months of effort in typical project schedules.

Unified Debug based on Synopsys' Verdi3 environment provides a consistent debug user experience across the verification flow, optimised with Verification Continuum technologies for even higher productivity. Verdi3 provides a single interface for multi-domain debug across virtual prototyping, static and formal verification, simulation, emulation and FPGA-based prototyping. Since bugs may exist on the boundary between traditional verification domains, Verdi3 also enables fully synchronised, mixed-abstraction debug between SPICE, RTL, transactions and software.

As SoC complexity and software content increase, leading SoC development teams have concluded that commercial FPGA-based hardware-assisted verification is the best, most scalable approach to meet the growing demand for high-performance platforms for early software bring-up and SoC verification. Verification Continuum integrates FPGA-based emulation and prototyping seamlessly into mainstream verification flows, helping to save weeks to months in design bring-up time compared with earlier approaches. Verification Continuum's Unified Compile technology has been architected to support FPGA-based verification platforms, delivering up to 3X faster compile time for Synopsys' ZeBu Server-3 emulation system.

Early availability is scheduled for December 2014, with general availability in 2015.





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