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Five hurdles to FPGA-based prototyping

Posted: 01 Oct 2014 ?? ?Print Version ?Bookmark and Share

Keywords:FPGAs? ASIC? SoC? prototype? partitioning?

Shortly after the introduction of FPGAs in the late 1980s, engineers seized upon these devices for developing system prototypes of ASIC and SoC designs. Containing vast amounts of configurable logic, these versatile components were a natural choice for building and testing the latest designs. As designs grew in both size and complexity, FPGAs also grew to provide ever-increasing (equivalent) gate counts.

With earlier generations of FPGAs, it often took a large array of devices to fully accommodate a logic design. However, using today's devices with their mega-million gate counts, it may require only a handful of devicesor even just oneto implement a complete design.

The utility of a working FPGA prototype is undisputed. It allows hardware designers to develop and test their systems, and it provides software developers early access to a fully functioning hardware platform.

Figure 1: A prototype is used to develop both hardware and software iteratively. Exploring their interactions often has implications for the original system specification.

There are a number of key advantages that FPGA-based prototypes provide. These may be summarised as follows.

Beyond the limit: At some point, software-only simulations hit the limit in terms of speed and capacity needed to run the latest designs effectively. If accurate software models are not available, prototyping may be the only option.

Ahead of the silicon: An FPGA-based prototype can provide a functioning hardware platform long before silicon is available. This enables early software development tasks such as OS integration and application testing. Only a hardware prototype will run fast enough for practical software development.

Ideal test platform: For designs that rely heavily on commercial IP, an FPGA-based prototype is an ideal test platform for ensuring all IP components perform together.

Seeing is believing: FPGA prototypes can provide a demonstration vehicle for downstream customers, providing confidence the system is functioning as specified.

Five challenges
Despite the advantages provided by FPGA-based prototyping, there are some significant hurdles to overcome. The five challenges presented below surfaced early on, and they haven't changed much over the years.

1. Design partitioning: Not many designs fit in a single FPGA; designs often must be partitioned across several devices. Initially, there were no tools to automate partitioning, so this task was tedious and error-prone. Worse still, designs that are split arbitrarily among several devices require a great deal of interconnect, which quickly surpasses the number of I/O pins available. Solving this problem requires a pin-multiplexing scheme.

Figure 2: Logical connections at the RTL level become a network of physical connections due to design partitioning.

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