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How to quantify serial link performance

Posted: 03 Oct 2014 ?? ?Print Version ?Bookmark and Share

Keywords:data transfer? hard drive?

SSD benchmarks are used to identify the data transfer rates of hard drives. However, it is all too often forgotten that the data transfer between controller and hard drive plays as important a role as the properties of the hard drive itself.

The SATA specification defines a data rate of 6 Gbit/sec. 8b/10b encoding of the transmitted data leads to a 20% overhead that is not used for user data. The protocol also requires extra bandwidth to compress the data into the Frame Information Structure (FIS). The underlying assumption is that all data is transmitted without errors. To detect individual errors and to verify the transmission, the SATA specification defines a Cyclic Redundancy Check (CRC) error detection code. While CRC is very efficient, it can only detect errors, it cannot repair them. So, if an error occurs, the data transmission has to be restarted.

The theory
To prevent the data transmission from needing to restart, the specification defines clear attributes for the signals. For instance, the signal frequency on the circuit board and the connector is specified at 3GHz (6 Gbit/sec). At these frequencies, PCB routing must follow specific rules. But, it is no longer enough to simply follow high speed routing rules. Various tricks are applied on the chips to optimise the transfer and the behaviour of the controller modules also needs to be aligned with the routing. On the driver side, pre-emphasisa kind of signal pre-distortion is used to compensate for the characteristics of the transmission line from transmitter to receiver. A typical SATA transmission line consists of the PCB routing, at least two connectors and a cable. This line forms an RC combination that acts primarily as a low-pass filter. However, the exact properties of the filter vary from system to system. By adjusting the strength of driver and pre-emphasis, it is possible to align chips and system. The driver strength also influences the absolute signal strength, while pre-emphasis adjusts the strength for non-transition bits, i.e. bits that do not follow a transition.

PCIe Gen3 provides a complex algorithm that lets the transmitter and receiver negotiate the best settings. The SATA specification is not as flexible, so it is up to the chip makers to decide on the level of flexibility to incorporate, and up to the board manufacturers to take advantage of this flexibility to optimise the system. Today, it is no longer enough to pre-distort the signals simply on the driver side; the signals also need to be post-processed at the receiver side using equalisation. Again, there are different settings for an optimum alignment of systems. Ideally, the device (SSD) and host (motherboard) manufacturers each handle this by compensating for the characteristics of their boards. The properties of the connecting cables are also clearly specified, so that it is possible to build an optimised system.

Hardware manufacturers use so-called compliance tests to verify signal quality. For this, the controller is put into test mode and drives clearly defined test patterns which are evaluated with an oscilloscope. Since the introduction of the third interface generations (USB, PCIe and SATA) compliance needs to be tested both on the side of the transmitter and the receiver. In the latter case, the worst permissible signal is sent to the receiver which rates the signal and sends the same information back (loop back mode). The information is then evaluated by a bit error rate tester (BERT) and compared with the transmitted data. The hardware required for this rapidly reaches the value of a reasonably-sized family house.

If the expense is spared, the systems usually work but fail to achieve the full performance that one would expect. The error detection of the SATA interface is very effective, so it is rare for an error to go undetected. However, the repetitions require bandwidth and if there are too many of them, the usable bandwidth can be significantly reduced.

Measuring the practical impact
To show the effects, a congatec test system with an Intel Series 7 controller was used to determine the write bandwidth depending on the transmitter setting. To ensure comparability with tests published by the trade magazine c't an IOmeter and the same settings were used. The test object was a Samsung SSD 840 Pro. In addition to the high transmission rates of the SSD, a reason for this choice was that Samsung uses SMART so that the interface CRC count for 0xC7 is also reported. Alternatively, this information would also be available via the PCH registers or the Windows Event Viewer. While IOmeter also gives an error count, this only kicks in when the controller loses the connection to the hard drive.

Figure 1: CRC error vs transmitter settings.

For the tests, the settings of the output driver were modified as follows: The signal strength was changed from 994 mV to 1325 mV and the pre-emphasis set to vary between -2.2 dB and -8 dB. The same tests can be done by modifying the receiver settings (receiver equalisation), but in this case the changes cannot be graphically represented.

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