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ST debuts ARM Cortex-M7 core-based MCU

Posted: 26 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:STMicroelectronics? MCU? ARM Cortex-M7? FPU? DSP?

STMicroelectronics has introduced the STM32 F7 microcontroller (MCU) series that the company said leverages the ARM Cortex-M7 core, just announced by ARM as its latest and most powerful Cortex-M processor. The MCU leapfrogs the industry's previous high-performance 32bit Cortex-M champ, STM32 F4, in providing up to twice as much processing and DSP performance that is accessible via a seamless upgrade path, the company indicated.

The STM32 F7 MCU series operates at frequencies up to 200MHz and uses a 6-stage superscalar pipeline and floating point unit (FPU) to produce up to 1000 CoreMarks. Architectural innovations surrounding the MCU boost performance and ease of use: ST has included two independent mechanisms to reach 0-wait-state performance from both internal and external memories: using ST's adaptive real-time (ART Accelerator) for internal eMBedded Flash and L1 cache for both execution and data access from internal and external memories.

STM32 F7

Manufactured on ST's robust and production-proven 90nm eMBedded-non-volatile memory CMOS process technology, the STM32 F7 series demonstrates ST's commitment to accelerate its own and customer innovation to meet time-to-market demands, the company stated. At the same time, the advanced, future-proof architecture offers significant headroom to deliver far greater MCU performance as the company moves to more advanced process geometries. The high-performance STM32F756NG MCU is sampling to lead customers.

Surprisingly, the higher performance of the STM32 F7 has not impacted power efficiency. Despite greater functionality, the series' run mode and low-power modes (STOP, Standby and VBAT) consume current at the same low levels as the STM32 F4: 7 CoreMarks/mW in Run mode and, for low-power modes, down to 120uA typical in STOP mode with all context and SRAM content saved, and 1.7uA typical in STANDBY mode and 0.1uA typical in VBAT mode.

In addition to ST's ART Accelerator and 4KB instruction and data caches, the STM32 F7 includes smart and flexible system architecture: an AXI and Multi-AHB matrix with dual general-purpose DMA controllers and dedicated DMA controllers for Ethernet, USB OTG HS, and hardware acceleration of graphics via ST's Chrom-ART Accelerator. Available in 512KB and 1MB eMBedded Flash to support applications that require large storage for code, the device features a large SRAM with scattered architecture: 320KB including 240KB +16KB on the bus matrix for shared data and 64KB of tightly-coupled memory (TCM) data RAM for critical real-time data; 16KB of instruction TCM RAM for critical routines; and 4KB of backup SRAM to keep data for the lowest power modes.

STM32 F7 peripherals also include an independent clock domain to enable system-clock-speed changes without impacting communication speed. The device also boasts a flexible external memory controller with up to 32bit data bus: SRAM, PSRAM, SDRAM/LPSDR, SDRAM, NOR/NAND memories. In addition, the STM32 F7 has a Dual Quad SPI interface for cost-effective memory extension even on lo- pin-count packages, and builds on the existing STM32 F4 series instruction set, delivering exclusively single-cycle multiply and accumulate (MAC) instructions and offering single-instruction multiple data (SIMD) instructions that work on 8bit and 16bit quantities packed into a 32bit word.

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