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Mentor Graphics, TSMC team up for 10nm FinFET designs

Posted: 30 Sep 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Mentor Graphics? TSMC? IC design? 10nm FinFET?

Mentor Graphics Corp. has joined forces with TSMC to address 10nm FinFET process requirements for early customers' test chip and IP design starts through the use of physical design, analysis, verification and optimisation tools. According to the companies, the infrastructure includes the Olympus-SoC digital design system, the Analogue FastSPICE (AFS) platform including AFS Mega, and the Calibre signoff solution.

"TSMC and Mentor are doing extensive engineering work that enables mutual customers to take full advantage of advanced process technologies," stated Suk Lee, TSMC senior director, design infrastructure marketing division. "Each node requires a tremendous amount of innovations to address new physical challenges, and to increase accuracy for customers' design enablement, while also providing increased performance and reduced turnaround time."

Calibre provides the layout pattern's full-colouring capability to help designers specify colour assignments independent of the design cockpit for 10nm rules compliance. For custom layouts, the Calibre RealTime product has been enhanced to enable interactive colour checking while designing with all leading custom layout tools, using foundry-certified Calibre signoff decks.

Mentor and TSMC have also enhanced the Calibre fill solution for 10nm FinFET designs. The SmartFill ECO functionality in Calibre YieldEnhancer supports a "fill-as-you-go" flow ensuring that IP and other design blocks are accurately represented as the design progresses. When part of the design is modified, the SmartFill ECO feature can re-fill just the affected portions to cut turnaround time. Likewise, Calibre LVS has been improved to maintain design hierarchy for efficient post-layout simulation at advanced process nodes such as TSMC's 10nm, the companies indicated.

The collaboration also makes the Mentor Olympus-SoC place and route system ready for TSMC's 10nm FinFET requirements. Significant enhancements have been made to the database, placement, clock tree synthesis, extraction, optimisation and routing engines to make them 10nm FinFET compliant, added the companies.

To ensure accurate circuit simulation of 10nm FinFET devices, Mentor collaborated with TSMC to validate BSIM-CMG and TMI models for high-speed device and circuit level simulation on the Analogue FastSPICE Platform, including AFS Mega. Recent 10nm FinFET models are also supported by Calibre xACT extraction product and the Calibre nmLVS product.

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