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The need for high data throughput in automotive apps

Posted: 07 Oct 2014 ?? ?Print Version ?Bookmark and Share

Keywords:infotainment systems? GPS? smartphone? Quad SPI? memory interface?

Embedded designers are increasingly tasked with enabling more functionality in embedded applications to deliver feature-rich and highly interactive user experiences. A good example of this is the evolution of electronics technology within automobiles. In the past years we've seen a complete transformation where things like digital dashboards and infotainment systems that control temperature, entertainment and more, have become the norm. A next step will be head up displays and highly advanced instrument clusters enabling apps in the connected car and thus effectively acting as your smartphone in the car. There will be the familiar controls for radio and navigation, along with new features for self-parking, advanced GPS and more. For this you need crisp 2D and 3D graphics on the display which again require fast processing.

High performance as well as cost and space saving
Especially in the automotive industry, the growing demand for infotainment and connectivity drives designers not only to go for higher performance solutions but also to lean on the cost and space savings side. Up to now, they have been able to take advantage of parallel NOR devices for performance. The industry is transitioning to serial peripheral interface (SPI) memories to take advantage of the low signal count and systems with a Quad SPI (QSPI) NOR memory can even achieve up to 80 MB/s data throughput using a single (DDR) QSPI memory with a so called data learning pattern (DLP). DLP is a Spansion-patented technology and, currently, only Spansion QSPIs with DLP can achieve these rates. Two QSPI devices would double the data throughput to 160 MB/s. These SPI memories retain compatibility with the original interface specified over 25 years ago. However, as the system-level read throughput continues to demand ever increasing speeds, a new look at the embedded memory interface offers a solution.

Figure 1: The universal footprint of HyperFlash eases the migration from existing QSPI designs to a faster performance and allows system applications to be scaled to different levels of flash performance when paired with compatible controllers, so different product models can be offered with a single design.

A new interface accelerates data throughput
Using a high speed interface such as the Spansion HyperBus Interface used by Spansion's HyperFlash memory, the data throughput can be accelerated up to 333 MB/s. This is more than four times the fastest Quad SPI flash currently available today with one-third the pin-count of parallel NOR flash.

The HyperFlash memory pinout overlays nicely onto the dual QSPI pinout, which makes the migration path for designers from existing QSPI designs to a faster performance as easy as possible and offers a fast back-up solution. It also allows system applications to be scaled to different levels of flash performance when paired with compatible controllers, giving OEMs the ability to offer different product models with a single design. HyperBus implements a low pincount bus interface with a simple read/write protocol which is suitable for both memories and peripheral interfaces. Especially for instrument cluster applications and displays with high resolution, instant-on GUI requirements, this technology enables the balance between system performance, cost and space efficiency. In combination, the Spansion HyperFlash Memory can be a solution to some of the bandwidth issues that have confronted NOR users in the past.

Comparing pin count and read throughput
Two of the most significant criteria used to evaluate NOR Flash devices are the sustained read throughput and the number of pins required to implement the bus interface. Comparing different NOR Flash devices and their respective active signal counts we find, that all legacy parallel interfaces require between 30 to 40 pins (figure 1). The SPI interface has evolved to use a 6 pin QSPI variant that has gained favour when enhanced read throughput is required. The HyperBus interface uses only 12 pins and marks a siginficant improvement delivering higher data throughput than QSPI while using only 6 pins more.


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