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The need for high data throughput in automotive apps

Posted: 07 Oct 2014 ?? ?Print Version ?Bookmark and Share

Keywords:infotainment systems? GPS? smartphone? Quad SPI? memory interface?

The HyperBus Interface delivers a substantial improvement in read throughput compared with legacy NOR flash interfaces (figure 2). With an 80 MB/s read throughput, QSPI has reached performance levels comparable with the asynchronous and page mode interfaces. Parallel NOR burst mode offerings come in around 133 MB/s with environments that expect a mix of wrapped and continuous read transactions. The HyperFlash memories leveraging the Spansion HyperBus Interface provide a new standard for performance by delivering 333 MB/s using a 12-pin interface. The 333 MB/s is achieved with the 1.8 V version of the interface; the 3 V version runs at 100MHz and provides 200 MB/s.

Figure 2: Comparing the pincount of the different Flash memory types.

Spansion's current NOR flash family of HyperFlash memories includes 128-Mb, 256-Mb and 512-Mb products. These initial offerings are compatible with either 1.8-V or 3.0-V operating voltages. Engineering samples of the 512-Mb device are available today with fully qualified parts available in the third quarter of 2014. The 128-Mb and 256-Mb HyperFlash densities will follow in early 2015. Spansion will develop higher or lower densities depending upon market demand.

Figure 3: Compared to legacy NOR flash interfaces, the HyperBus Interface offers a significant increase in read throughput.

The HyperBus Interface was developed to satisfy the need for higher performance while remaining sensitive to the pin-count constraints of modern microcontrollers. The philosophy behind it was to create a simple burst mode, read/write interface and transaction protocol that can be used by both memories and peripherals. The IOs are derived from LPDDR1 for the 1.8-V HyperBus Interface and from legacy NOR for the 3.0-V HyperBus Interface. Nothing exotic has been deployed, just an optimal usage of existing, market-tested signalling technology.

The Spansion HyperBus Interface has the ability to satisfy the memory requirements for both volatile and non-volatile memories in a large swath of high-performance applications. Although Spansion's focus is to place memory on the HyperBus Interface, the bus protocol is intended to be general purpose, leaving open the possibility for the introduction of non-memory peripheral devices.

The HyperBus technology has major implications for the automotive space. This speed allows for much faster boot time, direct execute-in-place from flash and less code shadowing, reducing the amount of RAM needed. For the consumer, this means more functionality, interactivity and performance out of the applications they're using.

About the author
Hiro Ino is Senior Director of Product Line Management, Flash Memory Group, Spansion. Mr. Ino's experience in the hi-tech industry started as a system design engineer being part of a development team for designing 3D-graphics supercomputers at Evans & Sutherland. Through his career, his contribution has evolved from engineering and engineering management to business management. Among his latest experiences include: Senior Director of Strategic Business Development at SanDisk, VP of Marketing and Business Development at m-systems (which was acquired by SanDisk), VP of Marketing at T-RAM Semiconductor, a high-profile venture-backed start-up developing a novel high-performance RAM technology, and Director of WW Memory Business at Sony Electronics developing ultra-high-speed memory for CPU cache applications. Mr. Ino received his degrees in Electrical Engineering and Computer Sciences from the University of California at Berkeley.

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