Effects of copper stress on smart power technology

SPT7, a smart power technology developed by Infineon Technologies, suffered massive yield loss for over-voltage detection parameters. The yield loss is about 30 per cent, with a major cluster in the middle of the wafer when tested at 150°C. However, only wafers produced in our Kulim plant encountered such issue, and the same design running in FAB1 was not affected.

Figure 1: FGA inFAB2 lot shows massive failure for over-voltage test, where the child lot FGA in FAB1 shows comparable results with FAB1 lots.

Figure 2: Wafer Bow measurement vs. over-voltage (left axis) and bandgap voltage (right axis) (a) pre anneal (b) post anneal 250°C at ambient environment 45 minutes.

Figure 3: FGA annealing temp at 440°C shows comparable results with FAB2 lots.

We then carried out further analysis through process block partitioning and loop lots to FAB1. It showed that our ECD block (forming gas annealing process FGA) contributed to a higher failure rate (figure 1). Split was performed on pre and post baked wafer to analyse the influence of temperature on these failing parameters. After anneal 250°C, wafer bow will become tensile due to the recrystallisation of copper. The wafer bow measurement and test measurement was taken during the pre and post anneal process to analyse the correlation of temperature on stress and over-voltage measurement. The tensile stress induced by the copper recrystalisation cause the wafer bow to increase as shown figure 2. Furthermore, a temperature split was done in the FGA process, and tests at 400°C (standard FGA temp), 420°C, 430°C and 440°C were performed. The wafers were measured immediately after the annealing. The result showed that 440°C is saturated and comparable with the RGB wafers as shown in figure 3.

Figure 4: C11 original layout, X15 partial power copper coverage of main bias on right side; X16 power copper coverage of main bias on left side.

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