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Synopsys, TSMC boost design solutions for 16FF+ process

Posted: 02 Oct 2014 ?? ?Print Version ?Bookmark and Share

Keywords:16FF+? custom design solution? GUI? schematic and simulation environment?

Synopsys Inc. and Taiwan Semiconductor Manufacturing Company (TSMC) have teamed up to develop an expanded 16FF+ custom design reference flow using Synopsys' custom design solution.

The partnership aims to improve methods for design constraints management, estimation of layout-dependent effects prior to final layout, schematic-driven layout with FinFET devices, a simplified method to run pre- and post-layout simulation, and a streamlined graphical user interface for layout of matched devices and guard rings.

In 16FF+ design, circuit designers need a smooth path for communicating constraints to the layout designer. Design constraints such as device matching, colour assignment, symmetry and clustering can be added to schematics and passed to the layout editor to be enforced during layout. Additionally, the schematic environment has been updated with a simplified method for running pre- and post-layout circuit simulation and comparing the results. Speeding the analysis of layout parasitics reduces the time it takes to finalise the layout. The schematic environment has also been enhanced to support a schematic-driven layout flow for FinFET devices.

In analogue circuits, good device matching is needed to deliver performance margin and production yield. The matching device creator in Laker makes it easier to achieve quality custom layout with updated support for matched placement of FinFET devices. Now, density-aware device array placement, guard ring creation and dummy insertion are all handled through a graphical user interface (GUI). For analysing layout-dependent effects, the custom design reference flow with Laker and TSMC's LDE-API provides a smooth path for back-annotating extracted device parameters to simulation after placement is completed.





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