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How to improve FPGA comms interface clock jitters

Posted: 16 Oct 2014 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? phase-locked loop? PLL? SerDes? IP?

This particular PN plot shows that this PLL technology meets even the tightest 1G end-point specifications with enough margin for the embedded designer to feel confident the system will be robust with the benefit of even lower power. This example shows that a 100MHz clock frequency commonly used for 1G and above applications coming in at 622fs over a 12kHz to 20MHz mask including spurs is typical performance of the PLL technology used in the VersaClock 5.

Products like IDT's VersaClock5 offer embedded designers versatility and much lower power. There are quite a few trade-offs in PLL design; it is very difficult to design a PLL that has both the highest possible performance and the lowest possible power. The FemtoClock NG PLL technology supports best in class performance, but is slightly higher power than the VersaClock 5. VersaClock 5 was designed to provide enough performance to meet all 1G and above common protocols up to 10G (end-point depending) and still offer best in class power consumption and versatility.

Figure 4: Phase noise plot C typical phase noise at 100MHz (3.3V, 25C).

Routing the clocks
Typical applications involving FPGAs and ASICs can have multiple CDRs and SerDes blocks performingfor example, gigabit Ethernetand typically, they aren't always in the same place. CDRs are placed in different areas within the FPGA/ASIC in order to keep them isolated from noise generated by other IP. In many cases when designing around an FPGA/ASIC that requires gigabit Ethernet or 10 gigabit Ethernet, multiple copies of that clock may be required, one for each high speed CDR. In general that requires the generation and distribution of 156.25MHz, for example, for 10 GbE.

In the case where multiple copies of the clock are required, the embedded designer has a choice to use a clock generator device like the FemtoClock NG or the Universal Frequency Translator or even VersaClock 5 and, depending on how many copies of the same output frequency are needed, a low noise fan-out buffer may also be required. In the case where the ASIC or FPGA have multiple PHYs, the clock doesn't go to just one place on that FPGA/ASIC. It may go to four different places and a lot of times on opposite ends of the chip.

Therefore, the designer needs four copies of that low noise clock. In this case, when an additional clock distribution buffer is added between the clock generator and the end-point (FPGA or ASIC), a bit more jitter is added, and it needs to be taken into account. Any logic (non-PLL) device like a fan-out buffer used to distribute clocks will add some additional jitter to clock.

Careful consideration must given to make sure the overall jitter budget defined by the FPGA, ASIC, or PHY is met at the input to that device. The fact that a clock distribution device could be used puts even more emphasis on the quality of the PLL within the external clock generator and even more margin must be budgeted for the clock source itself.

There are a number of very low noise buffers available from IDT that limit the amount of additive jitter through these parts, like the new 1.8V 8P34S1xxx family of low power LVDS buffers boasting lowest in class additive phase jitter typically 40fs or less. In the end, the end-point jitter requirements must be satisfied regardless of the number of buffers in the path of the PLL and end-point clock input.

About the author
Fred Hirning is Senior Field Applications Engineer at Integrated Device Technology (IDT). Previously, he served as digital design engineer at Quadic Systems and later as a Senior Applications Engineer for Tundra Semiconductor. Fred received his BSEE from the University of Hartford.

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