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Boost thermal management of electronic systems

Posted: 17 Oct 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Thermal management? Compact Thermal Models? CTM? Detailed Thermal Model? SupIRBuck Regulator?

Thermal management of electronic systems is becoming more important in a wide variety of electronic applications, such as computers, telecommunications equipment and semiconductor devices, as well as aerospace, automotive and consumer electronics. Compact Thermal Models (CTM) of electronic packages is needed in thermal simulations of electronic systems. A CTM does not disclose the IP information of a package and is preferred by electronic package manufacturers for use in their customers' thermal evaluation of electronic packages. On the other hand, a CTM consists of fewer elements than a Detailed Thermal Model (DTM) does, and hence needs less computation time in thermal simulation.

In 1989, an extension of the junction-to-case thermal resistance methodology created a thermal resistance network from junction to each distinct external surface of an electronic package [1]. In 1995, the DELPHI consortium published the first paper on Boundary Condition Independent models [2]. A lot of papers on this topic have been published since then. JEDEC also published standard of DELPHI Compact Thermal Model Guideline [3] and Two-Resistor Compact Thermal Model Guideline [4]. Many previous publications on this topic including the two JEDEC standards are presented for only single-die packages.

CTMs of SupIRBuck Regulators offered by IR are touted to give accurate temperature prediction for the three dies in the package. These CTMs are boundary condition independent. It means when boundary condition changes, e.g. with or without heat sink, or with different PCB layout under the package, the CTMs can predict the junction temperature rise within 5% difference or better from that of the DTMs.

These CTMs are also independent of power loss distribution inside package. A typical SupIRBuck Regulator wire bonding diagram is shown in figure 1, where Q1 is high-side FET, Q2 is the low-side FET and IC is control IC. In different application, the power loss distribution among the three dies is different. For example, when the switching frequency is higher, Q1 adds more power loss than Q2 does. Different input and output voltages and currents also have different impacts on the power losses of Q1 and Q2.

We use the power loss ratio of Q1 over Q2 together with the total power loss of Q1 plus Q2 to represent the different power loss distribution between Q1 and Q2. IC has only relatively small change in power loss for different applications. For these different power loss distributions, the CTMs of SupIRBuck Regulators can also predict the die temperature accurately in comparison to that of the DTMs.

Figure 1: Typical wire bonding diagram of a SupIRBuck Regulator.

The compact thermal model construction
This Compact Thermal Model consists of three parts: the lead-frame, the top-mould and the model core between them as shown in figure 2. The lead-frame is a metal part with some of ordinary moulding material; the top-mould is of ordinary moulding material.

Figure 2: Side view of the compact thermal model.

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