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Is concurrent engineering fit for FPGA power design?

Posted: 23 Oct 2014 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? power systems? concurrent engineering? bill of material? design tool?

Despite easy access to a variety of development tools such as early power estimators and power analysers specifically targeting FPGA-based projects, it is beneficial for power designers to consider a worst-case, rather than an optimal-case, power system early in the design process because there is still too much uncertainty in how the dynamic load requirements will fluctuate between a static, low current condition to a full processing state until the hardware design is completed and power can be measured.

Could adopting concurrent engineering (CE) practices provide a way for development teams that are using FPGA devices in their projects to more easily and quickly find and extract the most effective balance between processing performance, bill of material (BOM) cost, and energy efficiency in today's designs? Examining how concurrent engineering impacts a team's design efforts and how it can affect a development team's ability to address power supplies from the beginning of the project alongside the FPGA and the rest of the system can help answer this question.

Concurrent engineering is a mechanism that enables design teams to more quickly discover and resolve disconnects in assumptions between the various disciplines that work together to produce the final design. It is highly unlikely that any development team could get all of the requirements for a complex system perfectly correct at the start of a design C as a result, it is more effective to be able to discover, identify, and abandon disconnects in assumptions and design decisions as early as possible and replace them with ones that guide the project closer to the desired outcome at the lowest possible cost.

Is the complexity and potential consequences of late design cycle and worst-case FPGA power system design sufficient to justify adopting concurrent engineering practices? To answer this we need to understand: what are the sources of design complexity and uncertainty that designers of FPGA power systems face and how do they affect the trade-offs they must make when designing the power supply?

Complexity and uncertainty
Every member of a design team is experiencing increases in complexity and uncertainty C which are fortunately also being somewhat mitigated with improving levels of integration and abstraction which help keep the overall amount of complexity within the capacity of a human designer to understand and work with. As with any discipline that adds its contribution at the tail end of a design, upstream design assumptions and decisions can create additional sources of complexity and uncertainty that might otherwise have been minimised if there was earlier coordination and communication.

The design of the power supply is one of these potential downstream disciplines in increasingly complex systems. For this exercise, let's look at the sources of complexity and then uncertainty from the perspective of the power supply designer. The two key FPGA specifications that we will look at that affect the design of the power supply are voltage and current requirements.

FPGA voltage requirement trends are driving up complexity because they require a growing number of power rails. Instead of needing two power rails for core and I/O cells and possibly a third power rail for auxiliary functions, today's high-end FPGAs can require more than a dozen externally-driven power rails.

Why has the number of power rails needed grown so dramatically? SRAM cells may require a slightly higher voltage then the internal logic gates to ensure reliable full-speed operation while also using a lower voltage for standby mode. Industry standards can prevent different I/O cells from sharing the same power rails and increase the number of power rails needed because they may lock the various I/O cells and their physical receiving and transmitting interfaces to different power supplies with different supply-noise limits and voltage levels. For example, Ethernet may run at a different I/O voltage than an I2C bus. One is an on-board bus and the other is an external bus, but both can be implemented in the FPGA. Reducing jitter or improving noise margins for sensitive circuits, such as low-noise amplifiers, phase-locked loops, transceivers, and precision analogue circuits, can increase the need for more power rails because they cannot share a power rail with noisier components even though they are operating at the same voltage.

Besides requiring a growing number of power rails, today's FPGAs are operating at lower voltages than their predecessors which is valuable for reducing power consumption and increasing integration, but also increases complexity because the power supply must be able to maintain voltage tolerance requirements that keep getting tighter (figure 1). As an example, the published magnitude of the core voltage ripple tolerance for FPGAs based on 28 nm technology node has more than halved since FPGAs were manufactured in 130 nm. The percentage of error budget has shrunk from 5% to 3% and is heading towards 2%. Maintaining the voltage tolerance requirements is related to understanding and addressing the FPGA current requirements.

FPGA current characteristic trends are driving up complexity because the higher density and number of peripherals/functions/IP blocks contained within the FPGA is growing alongside Moore's Law C approximately twice as many blocks fit in the same amount of silicon between each technology node. While the voltages supplied to the FPGA are fixed, the operating current for each of these voltages is not and fluctuates depending on how the FPGA logic is implemented.

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