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ARM-based SoCs, IoT core take centre stage

Posted: 23 Oct 2014 ?? ?Print Version ?Bookmark and Share

Keywords:embedded? LTE? Cortex-A53? virtualisation? x86?

Expect the latest embedded SoCs, cores and buses to debut at the Linley Tech Processor Conference this week. The event's talks will cover the waterfront from carrier networks to the Internet of Things.

The rollout of LTE gave a boost last year to slowly growing embedded markets where Intel's x86 is the leading architecture, followed by the PowerPC. But multiple vendors are migrating to ARM-based SoCs, chipping away at PowerPC and MIPS-based designs, says Jag Bolaria, a senior analyst at Linley Group.

For example, Freescale added to its Layerscape family of embedded processors a new midrange ARM-based member, the QorIQ LS1043A. The chip, sampling early next year, uses four Cortex-A53 cores running at 1.5GHz to deliver more than 16,000 CoreMarks at 6W.

Freescale provides network virtualisation software for the chip, which targets branch office and industrial routers and control plane processors. Marvell will compete for sockets in similar systems with its first network search co-processor, the Questflo 98TX1100, sampling now.

 Freescale's latest QorIQ

Freescale's latest QorIQ rounds out its family of ARM-based comms SoCs.

Questflo can handle up to 2.4 billion searches per second and eight million flow entries. It executes one search per clock at a fixed low latency while running at 25W.

CAST Inc. will describe an ultra-low-power processor core for wearables and IoT systems at the other end of the network. Its 32bit BA20 can deliver 3.04DMIPS/MHz and 3.41CoreMarks/MHz. It can be compacted into a 0.01mm2 die delivering 2?W/MHz in a 40G process and is available now in RTL source code or an FPGA netlist.

Separately, ARM and the RapidIO group will talk about new interconnects for 64bit SoCs.

ARM will detail two new members of its cache-coherent, on-chip interconnect family using the AMBA 5 CHI. The midrange CoreLink CCN-502 links up to four core clusters and 8MB L3 cache at data rates up to 0.8Tbit/s. The high-end CoreLink CCN-512 connects up to 12 core clusters and 32MB L3 at rates up to 1.8Tbit/s.

For its part, the RapidIO community is starting a project to define an interconnect for 64bit ARM SoCs. AMD and ARM have joined the working group behind the effort, which includes Cavium, Freescale, IDT, Mercury Systems, Texas Instruments and Xilinx.

The cache coherent link aims to connect tens of sockets with tens to hundreds of cores. It will support GPUs and DSP, mappings to ARM AMBA interface protocols, and hooks to other standards such as OpenFlow and Open Data Plane.

- Rick Merritt
??EE Times

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