Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

Microsoft targets extensive FPGA role

Posted: 24 Oct 2014 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? Microsoft? data centres?

Microsoft is toying with the possibility of putting an FPGA on every server in its data centres, which could ease a very real pain point in the future.

The company runs more than a million servers, and it sees a network bottleneck coming sometime in the next three years, Kushagra Vaid, vice president of sever engineering at Microsoft, said in a keynote at the Linley Tech Processor Conference in California.

"We are in position now where none of the silicon providers can keep up with the rate of change in Azure," one of the largest of 200 workloads Microsoft's data centres run, he said. The networks need "new features for programmability, for flow control, [and virtual] switches. It's changing so fast the network silicon can't keep up with it, so that's raising the question of going with an FPGA."

Earlier this year Microsoft announced plans to use FPGA cards in a significant, but limited way to accelerate ranking of its Bing searches. The additional performance was greater than the cost of the custom Altera Stratix V cards the company designed.

Whether such a strategy will work to deliver new networking speeds and features remains to be seen. After his talk, Vaid was swamped by a handful of vendors pitching ideas for open APIs for FPGA accelerators and other concepts.

What's clear is the looming pain point. In the past four years servers in Microsoft's data centres have shifted from using 1- to 10- to (most recently) 40-Gbit/s interfaces. All new servers the company buys now use four 10G chips to send data at 40G rates to a top-of-rack switch, a rate most silicon vendors had anticipated to be used only for top-of-rack switches.

Not only must the network chips be fast, they are being asked to handle an increasingly wide array of functions.

For example, Vaid described the need to perform real-time encryption at 40Gbit/s rates on all data leaving any of its 15 global data centres.

"That's a huge amount of processing power. We have done studies showing it takes 16 of 24 cores in an Intel Ivy Bridge server processor... That's not very economical, so we have a need for offloading crypto. This is a whole new level of hardware design that needs to be done."

In addition, Microsoft has developed a way to replace with distributed software the load balancing function once handled by discrete appliances. It is exploring similar approaches to jobs such as deep-packet inspection. "This is the sort of thing people are calling network function virtualisation," Vaid said, referring to an industry standards effort at ETSI.

Microsoft has not evaluated CPUs with FPGA co-processors linked on a coherent interconnect with shared memory, an approach companies such as Intel and IBM are promoting. "But that's a whole different programming model, and it's not clear how you share data and control structuresI don't think anyone has figured that out yet."

Vaid challenged chip designers to come up with designs that can flexibly handle general-purpose jobs and accelerate dedicated tasks. He acknowledged that requires putting CPU- and FPGA-like capabilities in a single low-cost chip. Also on his wish list, an architecture that can change at the speed of today's data centre workloads.

"I was at Intel, and I know how long it takes to develop hardware," Vaid said. "We need to find a way to balance these two, or else we leave money on the table or the industry gets fragmented."

- Rick Merritt
??EE Times

Article Comments - Microsoft targets extensive FPGA rol...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top