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The lowdown on manufacturing RRAM

Posted: 04 Nov 2014 ?? ?Print Version ?Bookmark and Share

Keywords:resistive random access memory? RRAM? NAND? 3D? CMOS?

Non-volatile resistive random access memory (RRAM), widely considered by analysts and other leading experts to be the most viable alternative to NAND, offers clear benefits in cost, manufacturability, and gains in overall system performance. There is no question that current NAND technology has hit its scaling limits at the 1Y node. While 3D-NAND is considered to be the next alternative to NAND by enabling continuous cost reduction and scaling, the technology suffers from cell performance issues and poor on/off ratios, resulting in increased system complexity.

Challenges
In order for a technology to succeed in a 3D architecture, it must deliver a significant increase in density, with a lower cost per bit compared to current Flash solutions, and it must accomplish this with a cell that performs better than existing cells. If these two requirements are not met, a 3D memory will fail to meet the capacity, density, and cost expectations of customers designing next-generation products.

A typical, manufacturable 3D memory architecture must meet three prerequisites in order to be cost effective and scalable. First, the memory array must be monolithically integrated onto the control circuitry, using the smallest CMOS transistors possible, with the tightest metal pitch available at that technology node. It must take into account thermal budget considerations, so adding the memory cell does not impact the CMOS. Also when doing multiple layers, layers of memory cells on top should not affect layers at the bottom.

The second prerequisite of 3D memory is that it needs to be scalable. In order to achieve this, the memory must take into account both physical limitations and device performance issues for any cell that scales. Typically, scaling the cell to a smaller size degrades the performance metrics. This is especially true for electron-based devices.

Finally, the technology has to be stackable and easily integrated in a 3D architecture. This will enable memory manufacturers to deliver multiple terabytes of storage on a single chip.

Current efforts to implement 3D memory are based on scaling and stacking the existing 2D Flash memory cells. However, there are three key issues to overcome to effectively enable this approach. Since the 2D Flash cell is electron-based, and every cell has a finite number of electrons, controlling this cell to get a multi-level-cell (MLC) is difficult. To accomplish this task, the basic cell has to be improved, or the controllers have to become more complicated. Scaling this cell becomes more difficult as the number of electrons is reduced further. Thus the only way to increase density is through increasing the number of stacked layers.

If the current cells must be stacked to achieve density, the main issues become the cost of etching vertical trenches through 50+ alternating layers, along with custom tooling and increased capital expense for the fabs. The challenges for a 3D memory solution are summarised below in table 1.

Table 1: Challenges for a 3D memory solution.

Opportunities
Resistive memory technologies involving simple two-terminal devices can be integrated into backend metal layers to provide an elegant solution for meeting density, capacity, and cost challenges.

From a cell perspective, resistive memory elements boast the same on-current as the device area is scaled down but have reduced off-currents. On/off current ratios, from a few hundred to more than a thousand, are typical. This also improves the sensing margin, enabling both sensing with less complicated CMOS peripheral circuitry, and the ability to do MLC at smaller technology nodes. Filament-based resistive memory elements enable cells to be scaled to sub-10nm sizes.

Figure 1: Example of a multi-stack RRAM element integrated into backend metal layers.

Figure 1 shows an example of a multi-stack RRAM element integrated into backend metal layers. Two fab process parameters are critical to the devicethe thickness of the switching layer film (TSL), and the critical dimension (CD) over which the switching phenomenon occurs. Both of these are easily controlled with current state-of-the-art manufacturing tools for lithography, PECVD film deposition, and metal etch tools in today's 20 to 40 nm node fabs.

Stacking can be done very easily with resistive memory using backend integration.

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