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Rethinking memory design for IoT and wearables

Posted: 05 Nov 2014 ?? ?Print Version ?Bookmark and Share

Keywords:wearables? smartphones? NOR flash memory? multi-chip package? PSRAM?

Wrist radios have been staples in comic books and science fiction for decades, however it has been far easier for writers to conjure up the vision than for engineers to realise the technologyuntil now. If smartphones are now the ubiquitous embodiment of Star Trek's 'communicator', wearables such as smart watches, fitness bands, or even rings that turn your finger in a gesture controller, finally bring the latest gadgetry technology to the masses.

Yet wearables aren't merely an evolutionary change to existing mobile devices. Instead the physical dimensions and electrical requirements of wearables are so vastly different than smartphones that they constitute an entirely new hardware category. The disparity in physical size, battery capacity, and usage environment, where things like water and shock resistance are much more important, mean wearables bring a new set of design requirements and constraints. Developers can't just scale existing smartphone designs and expect to have a usable smart watch.

For example, compare two category leading products, the Pebble Smartwatch and the iPhone 5S, for stark contrast in packaging density. The former's case is a mere 43 x 34 mm or about one-fifth the surface area of an iPhone with its 4-inch screen. Within that 10-mm-thick package, Pebble's designers had to pack a 2.3-inch LED display and a single circuit board with memory, SoC controller, various sensors, Bluetooth chip, and battery. All of this on a double-sided circuit board where real estate for components and interconnect is at a premium and where buyers want the slimmest possible device profile.

The demands on wearable designs don't stop with the packaging. Due to limited space for batteries, products must be extremely power-efficient in both active and standby modes, yet start up instantaneously, support Bluetooth communications, and seamlessly run applications that engage the user. No one will buy a smart watch just to tell the time.

Mitigating the design difficulty is the fact that unlike in the comic books, no one expects a smart watch, connected glasses, or fitness band to replace a smart phone. Instead, smart phones are evolving into multipurpose hubs to which a growing constellation of wearable devices connect. This means most wearables don't require high-capacity, persistent storage or fast multi-core processors. Add up the capacity, size, and power requirements, and wearables are an ideal platform for NOR flash memory.

NOR flash is the perfect fit for wearables
In the days before smartphones capable of storing a season's worth of TV shows or an entire music library C that is, when mobile phones were just phonesNOR flash was the preferred persistent storage medium. Unlike NAND, which stores multiple bits in series, trading off random access for density and write speed, NOR behaves more like traditional DRAM, in which memory cells can be read and written individually instead of an entire block at a time.

This means NOR can be used for application code that can be executed in place without first being copied to a separate RAM cache. Random access also means NOR flash is capable of high-speed read throughput of up to 20 MB/s for serial (SPI) and 250 MB/s for parallel NOR designs.

The tangible benefits of choosing NOR flash over NAND in wearables are compelling. NOR flash's direct code execution greatly reduces boot time, meaning devices start up in an instant. Likewise, eliminating RAM needed for code execution means standby power consumption is much lower, yielding longer life when using the tiny batteries that are required in wearables packaging.

Since wearables are generally tethered to another device through which they regularly connect to Internet services and databases, they don't need to store much local data. Even a day's worth of health and fitness measurements is minuscule relative to the size of audio and video files. With physical space in wearables at a premium, NOR flash capacity and die size is much better aligned to application needs than NAND.

This next point may seem counter-intuitive since NAND flash arrays are much more dense than NOR. Indeed, since NAND flash is designed for the highest possible density, products typically use the smallest fabrication process nodes available, currently 16 nm.

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