Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Place-and-route tool speeds up silicon design

Posted: 30 Oct 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? Panasonic? multimedia? silicon? place-and-route?

Synopsys Inc. has revealed that its IC Complier II place-and-route tool allowed Panasonic Corp. System LSI business division (Panasonic SoC) to achieve silicon success with their high-end multimedia chip. According to the company, the IC Compiler II is a game-changing successor to the IC Compiler product, which the company regards as the industry's present leading place-and-route solution for advanced designs at both established and emerging nodes.

Key capabilities in IC Compiler II include rapid design exploration, unique clock-building, analytics-driven optimisation to boost quality-of-results and extensive use of multi-mode and multi-corner optimisation throughout the flow to accelerate turnaround time. The unique benefits it offered with five times faster implementation, IC Compiler II is also being used in other designs at 40nm and 28 nm process technology nodes.

IC Compiler II was built from the ground up to deliver a major leap forward in physical design productivity. Based on a multi-everything infrastructure and multicore technology that enables ultra-high-capacity design planning capability, unique clocking technology and advanced global and analytical closure techniques, IC Compiler II claims to deliver a ground-breaking 10-times increase in design throughput. IC Complier II's "analytically-global" optimisation provides faster, broader and more convergent physical synthesis and closure. This natively multi-threaded technique uses highly scalable timing and extraction engines that enable extensive multi-corner and multi-mode (MCMM) optimisation. Early and broad analysis enables optimisation for large number of concurrent scenarios, improving signoff convergence and reducing ECO iterations to a minimum. Additionally, patent-pending MCMM-aware local-skew clock construction techniques enable significant speed up in the building of complex clock networks with hundreds of domains and achieve the high-frequency clock requirements that are typical for the success of high-end chips.





Article Comments - Place-and-route tool speeds up silic...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top