Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Memory/Storage
?
?
Memory/Storage??

NVM IP for TowerJazz 180nm SL process tech

Posted: 03 Nov 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? NVM IP? CMOS? sensor calibration? TowerJazz?

Synopsys Inc. has released the silicon-proven DesignWare AEON few time programmable (FTP) trim non-volatile memory (NVM) IP for TowerJazz 180nm SL process technology. According to the company, the NVM IP combines high voltage generation and control circuitry using a standard CMOS technology without the need for additional masks or processing steps.

The IP operates from a single core supply, eliminating the complication of providing a separate voltage for NVM programming. The DesignWare AEON FTP Trim NVM IP provides the smallest area for precision analogue IC trimming and sensor calibration applications, in a similar footprint as one-time programmable (OTP) solutions with the advantage of reprogrammability, detailed Synopsys.

The reprogrammability advantage of the NVM IP enables designers to make in-field calibration updates, which allow end customers to make customisations and changes. The NVM IP includes necessary support and control circuitry including all high voltage generation and distribution required for programming to reduce system design complexity and IC area. It also supports up to 1Kb instances, up to 10,000 write cycles, and more than 10 years of data retention at a temperature range (-40°C to 125°C) for industrial applications.

The DesignWare AEON Trim NVM IP for TowerJazz 180nm process is available. DesignWare NVM IP is also available for multiple other foundries in 250-40nm process technologies.





Article Comments - NVM IP for TowerJazz 180nm SL proces...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top