Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Embedded

Determine acceptable jitter level in embedded design

Posted: 12 Nov 2014 ?? ?Print Version ?Bookmark and Share

Keywords:clock jitter? FPGA? microprocessor? C2C? EMI?

There are various clock jitter types, measurement methodologies, and corresponding specifications. However, most hardware designers don't have the time to research these, and the detailed nuances of clock jitter specifications can seem like trivial minutia to the board designer.

The designer is often more focused on the larger design task(s) at hand. Taking precedence are design tasks specific to FPGA logic, microprocessor complex, data plane switch fabric, control plane switch fabric, RF signal chain, power, interconnectivity issues, design simulation, modelling, etc.

So, the designer must assume that the reference clock jitter specifications from the various chip vendors are relevant for their intended use of these devices, and that they are also specified completely and correctly.

But without some basic guidelines to follow, the designer could over-specify the clock jitter requirements and add undue bill of material (BOM) cost to the design with more expensive clocks devices. Or, even worse, the clock jitter requirements could be under-specified and corresponding errors will increase beyond an acceptable error rate for the given application. This may not be determined until after performance metric testing of initial prototype boards very late in the development cycle, potentially impacting end product release schedules.

Table: Application relevance of jitter.

Most fundamental checkpoint
The first and most fundamental checkpoint for the designer to consider is the most relevant clock jitter type for the given application. The table summarises some jitter classifications by application type, and the corresponding specification qualifiers.

Period jitter is the most intuitively understood jitter. It's simply the deviation from the ideal (or mean) period, and it's the relevant jitter type for synchronous interface and logic design. Some examples include a microprocessor (mP) interface with a synchronous memory or a synchronous state machine design inside an FPGA.

As the clock period shrinks or expands, it can have a dramatic impact on either setup or hold time for a synchronous design. That's why period jitter is relevant for these types of applications.

High frequency jitter, and cycle-to-cycle (C2C) jitter in particular, is the relevant jitter type for spread-spectrum clocks. A spread spectrum clock has intentionally induced low-frequency jitter to alleviate EMI (electromagnetic interference) that traditionally is a concern in consumer electronics. But since spread spectrum is low-frequency jitter, it doesn't impact a C2C jitter measurement. For this reason, C2C jitter specifications can be used to quantify the jitter performance of a spread spectrum clock.

A close look at frequency domain jitter
It's important to pay special attention to frequency domain jitter and its applicability to high-speed serial communications. Specifically, the reference clock jitter requirement for high speed SerDes (serialiser/deserialiser) design is detailed. This is the least understood jitter type, and as a result the one most prone to some of the common board design pitfalls.

A phase noise (PN) plot, shown in figure 1, is typically generated by a spectrum analyser that captures the spectral content of a clock signaluseful for seeing the frequency characteristics of clock jitter. It is also useful for describing the randomness of phase fluctuations, which implies random frequency fluctuations, and which in turn implies random period fluctuations.

Figure 1: Phase Noise (PN) Plot is commonly used to represent the clock jitter in the Frequency Domain.

Therefore, a PN plot is a representation of random clock period jitter, but in the frequency domain. Mathematically, it is the power magnitude of the noise (i.e. jitter) of the clock signal relative to that of the clock's fundamental frequency F0 at certain frequency offsets FC from the fundamental.

1???2???3???4?Next Page?Last Page

Article Comments - Determine acceptable jitter level in...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top