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Characterisation of DDR memory system margins

Posted: 17 Nov 2014 ?? ?Print Version ?Bookmark and Share

Keywords:DDR? memory sub-system? DDR controller? PHY? I/O?

If you went to the recent MemCon 2014 in California, United States, where the exhibit floor was crowded and a full day of presentations covered all things memory, you could not help but surmise that memory is hot.

One recurring theme at the conference was whether there is a more efficient way to explore and characterise the margins of a DDR memory sub-system. That's not so easy when the DDR sub-system (DDR controller, PHY and I/O) is embedded within a chip and is responsible for managing the data traffic flowing to and from the processor and external DDR memory. The DDR memory interface normally is the highest bandwidth bus in the system, operating at multi-GHz data rates with read-write timing margins measured in picoseconds.

High-performance demands like these placed on the DDR memory system require that design teams thoroughly analyse and understand system margins and variations that will be encountered during system operation. Typically, there is limited or no visibility into the inner workings of the DDR memory sub-system, which creates challenge number one. Add to that the limitations of the JEDEC specificationit primarily addresses the behaviour of the DDR-SDRAM devices onlyand it's obvious something needs to change.

Device characterisation tools help, but only test and compare part-part variations. Ideally, DDR memory system designers want to be able to measure margins in-situ to fully and accurately understand system behaviour and gain visibility into possible issues as well as to optimise for performance.

MemCon attendees, the majority of whom are DDR memory system designers, want critical data on how their DDR system is performing. In an ideal design environment, they would like to easily be able to collect actual data from within the DDR sub-system using an automated approach that provides them a suite of analysis, visualisation and debug tools.

One solution that appears to be catching on is a DDR memory system analyser that provides the visibility they need. A special interface in the DDR PHY allows real time data to be captured from within the DDR memory system. It enables the tool to run numerous and different analyses to check the shape of the entire DDR memory system, including the package, board, and DDR-SDRAM device(s). It can be used to determine DDR memory system margins and identify board or DDR component peculiarities, or tune various parameters to compensate for issues that have been uncovered. The tool can characterise the performance of different boards and board layouts and compare the performance and margins of different DDR-SDRAM components. As well, it can help evaluate the performance and quality of different DDR SDRAM components from either different vendors and/or different speed grades.

So many DDR memory system designers have explained that DDR IP performance is defined now "in system," which makes its stability and reliability a guessing game. A true DDR memory system analyser should be able to give specific feedback to help improve the overall system.

Memories are central to system operation and performance and designers need a better way to look inside the memory sub-system to make sure that the system is optimised for production. That's why the DDR memory system analyser is drawing such interest.

About the author
Bob Smith is Senior Vice President of Marketing and Business Development at Uniquify. He began his career in high tech as an analogue design engineer working at Hewlett Packard. Since then, he has spent more than 30 years in various roles in marketing, business development and executive management, primarily working with start-up and early-stage companies. These companies include IKOS Systems, Synopsys, LogicVision, and Magma Design Automation. Bob was a member of the IPO teams that took Synopsys public in 1992 and Magma public in 2001. He received a Bachelor of Science degree in Electrical Engineering from the University of California at Davis and a Master of Science degree in Electrical Engineering from Stanford University.





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