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How to achieve 200-400GE network buffer speeds

Posted: 27 Nov 2014 ?? ?Print Version ?Bookmark and Share

Keywords:400GE? DDR4? ASIC? FPGA? transmission protocols?

To do so, the transmitter on the link computes a 6bit CRC code over the non-CRC fields (74 bits) of all outgoing frames, whether or not the frames need acknowledgement. The CRC code is generated from the following polynomial (1):

G(x) = x6 + x +1 (1)

The receiver detects errors in incoming frames by recomputing the CRC bits. When the receiver section of a port receives good frames, it issues an ACK. It also reports bad frames by piggybacking that information in the ACK bit of all outgoing frames, regardless of whether the outgoing frame itself is acknowledgeable. When a port detects a CRC error, that port transmits a replay request. The source port then replays all frames after the last good frame. In this way, the GCI interconnect recovers from errors that are detectable by the per-frame CRC code. Figure 3 diagrams the round trip pathway for CRC and ACK.

 CRC checking and acknowledgement

Figure 3: CRC checking and acknowledgement.

The transmitter and receiver on a link maintain a synchronised 8bit frame identifier (FID) counter for frames that need to be acknowledged. The transmitter section of a port includes a replay buffer to hold a copy of outgoing acknowledgeable frames. It can delete a given frame from the head of the buffer after the receiver section of the port receives an acknowledgment FID for that frame or for a later frame. When a link is carrying frames, the transmitter increments its FID counter by 1 for every acknowledgeable frame that it sends, as does the receiver. The process of serialising the FID over ACK bits is seen in figure 4.

 Serialisation of Acknowledgement FID

Figure 4: Serialisation of Acknowledgement FID.

The CRC code for a payload arrives one frame interval after the payload, and an error in the payload cannot be detected until the CRC code arrives. If performing an action based on the payload would have irreversible effects, the Transaction layer postpones action until after the Data Link layer has verified the CRC code.

The purpose of the CRC is to detect errors and recover with a replay. Without CRC, a potential catastrophic failure occurs when an error goes undetected and state in the memory is corrupted with an erroneous write. The probability of this is a product of the line rate, the Bit error rate and the "coverage" of the CRC. For an 80bit frame, the 6bit CRC in the GCI detects all single bit errors, all but 17 2bit errors, and 1233 of the 3bit errors. For SerDes implementations of chip-to-chip links, all that is required is a continuous-time linear equaliser (CTLE) and potentially a lightly weighted decision adaptive equaliser (DFE). This reduces the probability of a 2bit error to near BER2 and 3bit error to near BER3.

Doing the math outlined in Koopman [1] and assuming a very conservative bit error ratio (BER) of no more than 1x10-15 per lane (1.0E-18 is much more likely), the undetected error probably (UEP) is 1.7E-29 (1.7 x 10-29) per frame. The undetected error rate for 10.3125Gbit/s signalling is about 1.6E16 (1.6 x 1016) hours between failures, which is much lower than 1 Failure in Time (FIT or 1.0E9 (109) hours (150,000 years) over 8 lanes. In most systems, many other things will fail before an undetected error will occur. Future revisions of GCI may have the option for CRC-12 over two frames for the very conservative or much higher rate SerDes.

The GCI Transaction layer
The GCI does not define the transaction layer payload. The format and meaning of Transaction layer payloads is application-dependent. For example, a network processor and a memory device might use a master-slave protocol to communicate read and write commands and memory data. Alternatively, two ASICs might use a peer-to-peer protocol to stream long packets to each other. Figure 5 shows a transaction layer example.

 Transaction layer

Figure 5: Transaction layer example.

How GCI deals with transmission errors
Either residual PLL jitter or quantum effects cause random bit errors. For the GCI, the BER is guaranteed to be below 10-12, and in practical implementation in chip-to-chip interconnects, 10-18 . By comparison, the BER for parallel interconnects is 10-19 [2].

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