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Advances in FPGA-based prototyping

Posted: 01 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? prototyping? verification? ASIC? Partitioning?

A recent article, "Five hurdles to FPGA-based prototyping," explored some of the questions regarding FPGA-based prototyping and helped debunk the myths surrounding the issues of bring-up time, debug, performance, and reusability.

Over the next several articles, we'll look into the specifics of how FPGA-based prototyping can accelerate your design and verification.

There is a common misconception that FPGA-based prototyping is only suited to small designs and that the advantages of the technology diminish as designs grow. For verifying large designs, emulation is often the first technique that comes to mind. Now, emulation is fine for verifying large designs, but it comes at a cost. There is a penalty in both speed and price.

Emulation can be very slow at modelling your design, thereby impacting attempts at early software development. And emulation is expensive, putting it out of reach for companies on a budget. Every engineering manager is faced with considering time and cost trade-offs to meet stringent time-to-market windows. To put these trade-offs into perspective, let's first examine the advances in FPGA-based prototyping technology that help to close the gap between design size, speed, and cost.

FPGA technology advancements
FPGA capacity has increased exponentially over the years. Today's largest V7 FPGAs from Xilinx based on a 28nm process have the capability to hold the equivalent of up to 20 million ASIC gates. By using an array of such FPGAs, we can leverage this further, with the potential to build a system that is close to half a billion ASIC gates. And the next generation of FPGAs, such as Virtex-UltraScale based on a 20nm process, holds even greater promisethe prospect of building a practical and affordable system containing up to a billion gates.

FPGA-based prototyping can also run at much higher speeds than emulation. Internal FPGAs can run at hundreds of MHz, and I/Os can run at the multi-GHz range depending on the I/O standard. Even with very large FPGA prototyping systems, you can still expect anywhere from 5 to 20MHz system speed. This is an order of magnitude faster than emulation, which usually runs in the sub-MHz range.

To explore this idea of using FPGA prototyping for big designs further, let's look at the key technology considerations for adopting prototyping for these designs.

Partitioning is key when prototyping a large design using FPGAs. In the past, with smaller FPGAs, partitioning required cutting through an IP block and distributing it across multiple devices. Today, most design blocks easily fit within one FPGA, so partitioning is primarily the process of grouping select IP blocks together onto a single device. Furthermore, the adoption of new FPGA I/O technology such as 1GHz LVDS enables the interconnection of more I/Os between FPGAs using a pin-multiplexing scheme.


Partitioning software should also be considered. Along with other partitioning technology, the quality and usability of partitioning software such as Flexras and Mentor's Auspy have also significantly improved over the years. Similarly, the commercial partitioning tool from S2C has been used to partition a multi-core CPU design across 20 FPGAs.

Partitioning and implementing the design in multiple FPGAs doesn't mean much unless you have the ability to debug the design effectively and efficiently. Many debug tools, including those provided by FPGA vendors, can only be used on a single FPGA. This is okay if you only have a single FPGA design or if you have the time to debug each FPGA on your system separately. But this can be both time-consuming and highly error-prone. In addition, most of these debug tools utilise the FPGAs' internal memories, which results in very limited trace depth. Debugging a multi-FPGA design works better if you can look at multiple FPGAs at the same time. This reduces both debug time and errors, while also using external memory for increased capacity.

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