Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Embedded

Reduce power SoC consumption in the interconnect

Posted: 09 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:system-on-chip? SoC? interconnect? Modular? network-on-chip?

While power management has grown in importance for system-on-chip (SoC) developers, the one crucial area that is often overlooked is the interconnect. While most power management efforts focus on the computational aspects of the SoC, designers who adopt a more modular interconnect could reduce die size, alleviate routing congestion, and, by doing so, cut overall chip power consumption by as much as 0.7 milliwatts. A reduction this significant could be a game-changer in next-generation systems for mobility and power-conscious data centre applications.

The modular concept is different from other types of interconnects because it consists of a distributed architecture of switches, buffers, firewalls, pipe stages, and clock and power domain crossings. By using a universal transport protocol between all of the separate units on the chip, the modular approach enables designers to implement unit level clock gating to eliminate clock tree switching power where no traffic is present.

Modular on-chip network-on-chip (NoC) technology also reduces power consumption by localizing logic, minimising long wires, and keeping capacitance low. Designers who want to further enhance the power management abilities of their SoC design can explore measures to reduce the area and leakage power consumption of the chip by using the simplicity of a NoC transport protocol to serialise data paths and thereby minimise logic.

Low power consumption
The top level interconnect fabrics commonly used today typically rely on long wires that draw a disproportionate amount of power relative to the amount of logic area consumed on a chip. A clock tree is usually the greatest power sink within an interconnect, and clock gating provides the greatest potential for reducing this. Additionally, leakage power is the second greatest power sink, and reducing the logic area needed for the fabric can minimise leakage.

Designers considering a modular NoC interconnect will learn about the power and area benefits of the localisation of clock tree management, data path serialisation, and precisely located pipe stages.

Busses and crossbars: Brief history of interconnect
The history of interconnect fabrics shows how the philosophy of modular NoC design came to be, and addresses issues of scalability.

A SoC is a chip with a CPU and peripherals, and developers came up with interface protocol standards to link the elements together. With the advent of additional bus masters, connections to the peripherals were shared. Controlling access to the bus required a central arbiter, such as those used in board-level protocols.

 A shared bus

Figure 1: A shared bus with an arbiter shows how access control requires a central arbiter.

1???2???3???4?Next Page?Last Page

Article Comments - Reduce power SoC consumption in the ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top