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Calypto intros high-level synthesis tech to speed up design

Posted: 04 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Calypto Design Systems? high-level synthesis? design architecture? SystemC? C++?

Calypto Design Systems Inc. has uncloaked its third-generation, high-level synthesis (HLS) technology. Touted by the company as an industry-first, and based on customer input that resulted in a multi-year development effort, the Catapult 8 platform is built on a completely revised architecture that expedites design and verification closure, pushing the extensive adoption of HLS.

The Catapult 8 platform with the configurable hierarchical design architecture promises to deliver: control and predictability required to achieve design closure on complex designs; comprehensive design management and assembly systems with 10x capacity; integration with standard functional verification methodologies; power and verification optimised register-transfer level (RTL) code; and native dual-language support of SystemC and C++.

The Catapult 8 platform gives designers unprecedented control over which regions are optimised, and the ability to work "top down" or "bottom up," which is required to integrate RTL intellectual property (IP). The Catapult 8 database and smart caching techniques claim to provide at least a 10x capacity improvement, making the synthesis of large subsystems possible. The synthesised RTL is now optimised for power and verification requirements, in addition to meeting area and performance constraints. Verification-optimised RTL is code that is ready to be deployed into industry and corporate standard verification flows, including flows based on universal verification methodology (UVM). In addition, the architecture was expressly built to natively support both SystemC and C++ as input languages.

The selection of SystemC or C++ as the input language for HLS is driven by the design flow employed, as well as by some technical differences between the languages. As a result, it is becoming common for both languages to be used within a company. The new native dual-language capabilities for SystemC and pure C++ found in the Catapult 8 platform let companies standardize on a single HLS platform that meets the demands of different project teams.

Catapult 8 platform

Catapult: Product family overview

RTL verification is a major pain point for SoC design; adopting a high-level synthesis and verification methodology alleviates some of the pain by speeding simulation by 1000x and accelerating verification and debug. The Catapult 8 platform extracts design knowledge during synthesis, and optimises the RTL to maximise verification coverage when running simulations derived from C++ or SystemC coverage tests. Using the Catapult GUI, the user can also relate RTL structures back to the C++ source, allowing them to write additional coverage tests when verification holes are identified. The result is that Catapult 8 dramatically cuts the cost of both functional coverage and structural coverage, enabling teams to achieve verification closure much faster, stated the company.

Reducing power is becoming an essential design objective for many applications. Addressing low power requirements during high-level synthesis can provide significant power savings. Catapult 8 looks deeply through the design across clock boundaries, while the user explores alternative microarchitectures to determine optimal design solutions to achieve power, area and performance goals, the company added.

Available with the Catapult 8 platform is the Catapult Catware library, an extensive source code library of synthesisable functions such as filters and FFTs, provided in SystemC and C++. Paramaterisable and easily configurable, Catapult Catware enables design team to quickly create highly effective design code for high-level synthesis. Both the Catapult 8 platform and Catapult Catware are available.

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