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8bit MCU IP core enables faster design for HC11

Posted: 04 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Digital Core Design? MCU? IP core? HC11?

Digital Core Design (DCD) has announced the D6811E IP core aimed at IoT sensors and beacons. Boasting binary compatibility with the industry standard Motorola 68HC11 8bit MCU, the IP core can also be implemented in barcode readers, hotel card key writers, robotics and various embedded systems, added the company.

The DF6811E is a redefined 8bit MCU IP core, with highly sophisticated, on-chip peripheral capabilities and has an improved FAST architecture. According to DCD, it is nearly four times faster when compared to the original implementation. In the standard configuration, the core has integrated on-chip, major peripheral functions in one of below configurations: 68HC11A, 68HC11D and 68HC11E.

The D6811E implements two serial interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main 16bit, free-running timer system has three input capture lines, five output-compare lines and a real-time interrupt function. An 8bit pulse accumulator subsystem can count external events or measure external periods. An illegal opcode detection circuit, provides a non-maskable interrupt, if illegal opcode is detected. Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power.

The DF6811E MCU core can be equipped with the ADC controller, which allows using an external ADC controller with standard ADC software. The ADC controller makes external ADC's visible as internal ADCs in original 68HC11E MCUs. The DF6811E has built-in real time, on-chip hardware debugger, DoCD, which enable easy software debugging and validation.

The DF6811E is a silicon proven and fully customisable solution. DCD delivers it in the exact configuration, which allows the licensee to save his time and money (there's no need to pay extra, for not used features and wasted silicon). The package includes also fully automated test bench with complete set of tests to validate it at each stage of SoC design flow.





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