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Clash of FPGA devices expected for 2015

Posted: 05 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Altera? FPGA? Intel? Altera? Xilinx?

Intel, Altera and Xilinx are some of the companies developing and pushing to market their respective FPGA devices by next year in a flood of promotional claims and counter-claims. With this scenario, one can only imagine that the FPGA market in 2015 will be anything but boring.

Let's start by recalling what happened during 2013 when both Altera and Xilinx rolled out their 28nm families built by TSMC. Xilinx held the accolade of having the largest device (XC7V2000T) with nearly two million equivalent LUTs. This part is built using 2.5D packaging technology and was dismissed by John Daane, CEO of Altera, as a limited volume prototyping device. No doubt ASIC prototyping is not a huge market, but add military, high performance computing and applications such as scientific and financial acceleration, and the volume builds up. Why this is significant will become clear.

TSMC was offering a planar 20nm process in 2013, but the industry was sharply divided by the perceived benefits of this technology. In fact, some companies such as Nvidia stated that a 20nm process is of no benefit, as the tooling and wafer costs are both higher than 28nm with the result that there is no reduction in cost per transistor.

Having said this, Altera has created a mid-range Arria 10 family using the TSMC 20nm process. But it decided to skip using the 20nm node for its Stratix family in favour of focusing its engineering resources and moving straight to using the Intel FinFET process at 14nm for its next generation high-end product. This looked like an inspired move at the time, because Intel was widely reported as being two years ahead in terms of process technology. Intel was also producing devices at the 22nm node using the technology that it calls Tri-Gate. This strategy would give Altera a lead over arch-rival Xilinx that promised to be nearly insurmountable.

In contrast, Xilinx embraced 20nm for both the mid-range Kintex and high-end Virtex families using an architecture that it called UltraScale. The company shipped its first 20nm product to a customer in late 2013 and has continued the rollouts through 2014. The largest 20nm Virtex part is slated to have 4.4 million LUT equivalents. Now, probably few reading this column will be using the "biggest" and "baddest" FPGAs, but the top customers that both Altera and Xilinx service do use them. Applications such as communications, defence and data centres will use a range of complexities, and half of the revenue of the FPGA industry is in the high-end product ranges. So, if Xilinx has exploited the current situation fully, it should give it a big advantage, because once engineers gain familiarity with the latest tool flow they tend to stay with it for their next design (FPGA vendors call this "incumbency").

Meanwhile, Xilinx also committed to use the TSMC 16nm FinFET technology for products beyond 20nm.

It was initially planned for Altera to have samples around now, but the much publicised (and rumoured) race to get to production at 14nm has seen time frames for initial samples move into 2015. Altera expects the combination of the process and a novel HyperFlex architecture in Stratix 10 to double the performance of existing devices with significantly better power performance. They have also spoken of a monolithic device of over 4M LUTs, which would rival the Xilinx 2.5D device.

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