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Encryption core can be configured from 20-800Gb/s

Posted: 05 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Algotronix? encryption core? OTN? netlist? FPGA?

Generally, FPGA and ASIC companies depend on third-party intellectual property (IP) vendors to license cores for an entire range of circuit blocks. This sort of licensing happens because design teams don't have the skill set and/or time to develop their own implementations. The cores are typically offered as netlists with associated test benches against a fixed design.

This solution works well for cores such as memory controllers or a turbo encoder where the function is well defined, but encryption cores are somewhat special. These cores play a crucial part in system security and must not be compromised in any way. Customers want to be certain that the core does exactly what they want and includes nothing else, such as malicious code, but how can designers verify this with a netlist?

To address this issue, unlike just about every other IP you can license, Algotronix supplies the HDL source code for every licensed core such as its OTN AES-GCM core, which is configurable up to 400Gb/s. (You can actually go all the way up to 800Gb/s if you have access to a next-generation FinFET device.) In some respects, this is like leaving the door to the jewellery store open, but there are some good reasons for doing this in the case of an encryption core. The primary reason is that the design team must be able to prove beyond doubt that the code has no virus or Trojan code incorporated, and that it cannot be forced into unauthorised states or operations. The source code option cuts the cost and complexity of a security audit.

AES-GCM core

By delivering source code, Algotronix has always given designers the option to implement critical functional blocks in a choice of FPGA resources, such as LUTs or BRAMs, depending on what's available. This "mix-and-match" approach often allowed the design to fit into a packed chip, but the AES-GCM core goes way beyond that. Historically, customers could license one from a range of cores, say, for slow, medium, or fast data rates. By comparison, the AES-GCM-100G-OTN core can be configured to provide a throughput of any data rate from 20-800Gb/s. This 40:1 range is achieved by changing the clock frequency and adding progressively more pipelining to the design. This means that a single core can form the basis for adding encryption across a range of products. A piece of OTN equipment running at 20Gb/s might use the core in a lower-cost FPGA to provide duplex 10Gb/s connections, for example, while a 400Gb/s design would need to employ a faster, leading-edge device. Meanwhile, the 800Gb/s option is ready for when FinFET-based FPGAs are capable of pushing speeds higher at manageable power levels.

Finally, the AES-GCM core has been optimised to match the characteristics of OTN traffic, which allows the core to be smaller and consume less power than a general-purpose AES-GCM encryption core.

- Max Maxfield
??EE Times





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