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Verifying multi-processor SoC cache coherency

Posted: 17 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:system-on-chip. SoC? cache coherency? verification? multi-processor? GPUs?

The evolution from chip to system-on-chip (SoC) has brought value to both the engineering community and end users. With the move to greater complexity, problems that were once isolated to individual design blocks are now system-level concerns. Cache coherency is just the latest of these concerns. Every SoC team is facing or will face this challenge. Cache coherency interacts with many aspects of SoC functionality. Proper verification requires fast cycle-accurate models and coherency-aware randomized stress test cases.

The reason for this major change is the rapid evolution of chip design and verification. Most large, complex chips now contain at least one embedded processor and qualify as SoC designs. Most SoCs contain multiple processors (possibly heterogeneous), and most multi-processor designs now include caches to reduce memory latency and maximise system bandwidth. Further, in the latest generation of SoCs, designers are adding cache-coherent agents beyond the multi-processor clusters.

Cache coherency, long regarded as one of the most complex verification challenges, is no longer an issue for CPU developers only. This article presents a highly automated approach to cache coherency verification at the SoC level: generation of test cases to stress every aspect of a multi-processor, multi-memory, multi-level cache design. This solution requires no specialised knowledge of cache algorithms or of the underlying generation technology.

Industry evolution
Several factors are driving the industry towards cache coherency. The first is that embedded processor providers increasingly are shipping multi-processor clusters with built-in caches. Figure 1 shows a typical cluster available today, with four processors, each with its own dedicated Level 1 (L1) cache, and a Level 2 (L2) cache spanning them. Since these processors share a common memory space and have caches, coherency is required to ensure that the correct data is read from a shared memory location.

 A typical cache-coherent multi-processor cluster

Figure 1: A typical cache-coherent multi-processor cluster includes multiple cache levels.

Consider, for example, if one CPU writes an update to a memory location in its cache, and then another processor reads that same address from its cache. Without cache coherency, the read might return the old value of the location, rather than the updated one. Coherency algorithms might ensure that the update is written to the main memory, and that the second processor invalidates the cache line containing the memory address, so that it reads the updated value from memory.

If the only agents that need to be coherent are contained within a single cluster received from the processor vendor, then the SoC team may not need to think about the problem at all. However, SoC teams are increasingly connecting multiple clusters together, as shown in figure 2. The processor vendor may not provide a coherent connection mechanism for multiple clusters. Also shown in figure 2 are additional agents such as GPUs, DSPs, and I/O controllers that also may have caches and need to remain coherent with the CPUs.

 A new class of SoC designs

Figure 2: A new class of SoC designs includes multiple coherent agents.

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