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Examining structural faults that lead to glitches

Posted: 19 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:SoCs? IP? clock gating? glitch? mux?

With the increasing complexity of SoCs, multiple and independent clocks are crucial to their design. The design specifications require system level muxing of some of these clocks before they are sent to actual IP.

Also to save power, clock gating cells are inserted in the path of these clocks. While implementing these muxing and gating cells, designer tends to make some mistakes that can lead to glitches.

A glitch on a clock signal essentially renders a chip (or a section of a chip) to asynchronous behaviour. A glitch-prone clock signal driving a flip-flop, memory or a latch may store incorrect and unstable D (or data) input of a flip-flop, memory or a latch. This paper discusses structural faults that can lead to glitches in clocks. Also some bad design practice s that lead to glitches in data are discussed briefly.

Converging outputs of flops as clock
In the design of figure 1, the outputs of two flops converge through combinational logic to make the clock of the third flop. Here again we may have a glitch at the output of combinational logic leading to a glitch prone clock operating the third flop. Now the designer needs to carefully review such structures. We can give waiver to such a structure if we are sure that the toggling of both paths is mutually exclusive. A typical case could be where one of the paths is through static IOMUX registers. In that case we may waive the path.

 Converging outputs of flops as clock

Figure 1: Converging outputs of flops as clock.

Incorrect latching of enable signal
Clock gating is an age old and important technique to reduce the overall dynamic power of design. There could be multiple approaches to implement clock gating. In the clock gating cell of figure 2, the enable signal is generated as output of "and" gate. This may lead to glitch in the enable signal which may lead to erroneous (glitch prone) clock as input to the flop.

One must always ensure that the enable signal of any clock gating cell is output of a flop else we may see glitch in the enable. If such structures cannot be avoided it must be ensured that at least one input to the "and" gate is static when used (say driven out of some configuration register). This ensures that there is no glitch in the enable signal when it is used. Such structures can be caught with any structural verification tool or in gls.

 Incorrect latching of enable signal

Figure 2: Incorrect latching of enable signal.

Clock signals re-converging on a mux
In figure 3, the output of the mux after passing through the clock-pin of the flip- flop/latches re-converges back on the same mux. This results in creation of a glitch. We must ensure that we don't have such structures in our design.

 Clock signals re-converging on a mux

Figure 3: Clock signals re-converging on a mux.


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